k64388.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

1:	# check for SENDSAP
	li	    k1,SENDSAP
	bne	    k1,v0,1f

	# It is SENDSAP. Send address of savearea.
	la	    a0,savearea
	or	    a0,1		# indicate new format
	bal	    put_word
	b	    ice_loop

1:	# else. Not a special word.
	sw	    v0,(s0)		# save word in instr_buffer
	addu	s0,4		# ready for next word
	b	    ice_loop
	.end ice_loop

	.set at

/*************************************************************
*  get_cmd()
*	Get one word from the serial interface. The result goes
*	in v0.
*/
	.globl get_cmd
	.ent get_cmd
get_cmd:
	li	    k1,UART_BASE
	li	    a1,4			# get 4 bytes

	# wait for rxrdy
3:  lw      k0,OFFSET_status(k1)
	and	    k0,STATUS_RDY
    beq     k0,zero,3b

	# get the byte
    lw      k0,OFFSET_rxbuff(k1)

	# first byte?
	bne	    a1,4,2f			# br if not first byte

	# is the byte a wakeup?
	bne	    k0,ATTN,2f		# br if not a wakeup

	# wait for txrdy
1:  lw      k0,OFFSET_status(k1)
	and	    k0,STATUS_TXALMOSTFULL
    bne     k0,zero,1b

	# send an ack
	li	    k0,ACK
    sw      k0,OFFSET_txbuff(k1)
	b	    3b

2:	sll	    v0,8			# move word into position
	or	    v0,k0			# merge byte with word
	subu	a1,1			# bytecount--
	bne	    a1,zero,3b		# do next byte

	j	    ra
	.end get_cmd

/*************************************************************
*  get_word()
*       Get one word from the serial interface. The result goes
*       in v0.
*/
        .globl get_word
        .ent get_word
get_word:
    li      k1,UART_BASE
    li      a1,4

1:  lw      k0,OFFSET_status(k1)
    and	    k0,STATUS_RDY
    beq     k0,zero,1b

    lw      k0,OFFSET_rxbuff(k1)
    sll     v0,8
    or      v0,k0
    subu    a1,1
    bne     a1,zero,1b

    j       ra
    .end get_word

/*************************************************************
*  put_word()
*       Put one word to the serial interface. The word to be sent
*       comes from a0.
*/
        .globl put_word
        .ent put_word
put_word:
    li      k1,UART_BASE
    li      a1,4

1:  lw      k0,OFFSET_status(k1)
	and	    k0,STATUS_TXALMOSTFULL
    bne     k0,zero,1b

    sw      a0,OFFSET_txbuff(k1)
    srl     a0,8
    subu    a1,1
    bne     a1,zero,1b

    j       ra
    .end put_word

/*************************************************************
* 		End of interrupt-level code		     *
*************************************************************/


    .globl cpu_init
    .ent cpu_init
cpu_init:
/******************************************************************************
* Set the following in the Status Register (Coprocessor 0):                  
*   BEV      :	Exceptions in boot region (beginning of EEPROM - see below) 
*   CU0      :	Enable access to CP0 in user mode                            
******************************************************************************/
    .set noreorder
					                # clear the SW interrupt bits in the Cause Register
	mtc0	zero, C0_CAUSE			# only SW interrupt bits are writeable
	nop
    nop
	
	li	    a0, SR_CU0 | SR_BEV		# setup the Status register
	mtc0	a0, C0_SR			# load the CP0 register
	nop
	nop

    li	    a0, CCC_BGE | CCC_MUL | CCC_MAD | CCC_CMP
    mtc0    a0, C0_CCC		# load the CP0 configuration register
	nop
	nop
    .set reorder

/************************************************************
* enable PCI access to RAP registers
* this is necessary to avoid PC hangs when dipswitch 8 is off
*************************************************************/
    la	    t0,0xb0008160		# PCI Reg_Acc_En Register
	lw	    t1,0(t0)
	or	    t1,0x80
	sw	    t1,0(t0)		# set to allow snooping over PCI

/********************************************************************
* SDRAM power up sequence (via Memory Controller)
********************************************************************/

/****************************************
* Write Delay Config Register          *
****************************************/

	# Setup Delay Config Register to:	
	#	Sys/PLL Clock Delay    = 3.5 ns
	#       Read Clock Delay       = 0.0 ns
	#	Write Data Clock Delay = 0.0 ns

	#	SDRAM Clock Delay      = 0.5 ns
	
	li	t0,0x00000e01	# Fill t0 with Delay Config values
	li	t3,0xb0008204	# Delay Config Reg Addr -> t0
	sw	t0,0(t3)	# Set delay Config Register
	
	/*******************************************************************
	* Setup EEPROM, PHY, and SDRAM					   *
	*******************************************************************/
	
eeprom_pup:

/*********************************************************************
 * EEPROM Configuration (via Memory Controller)
 *********************************************************************/

	# Configure EPROM to:
                    #	Write High Time     [21:20] = 3 cycles
	#	Write Low Time      [19:16] = 4 cycles
	#	Read Recovery Time  [6:4]   = 3 cycle
	#	Read Time           [3:0]   = 4 cycle

	li	t0,0x00340034	# settings -> t0
	li	t1,0xb0008228	# EPROM Control Register -> t1
	sw	t0,0(t1)	# Configure EPROM

phy_pup:	

/*********************************************************************
 * PHY Configuration (via Memory Controller)
 *********************************************************************/

	# Configure PHY to:
	#	Mux                  [31] = 0  disabled
	#	Address Latch Enable [30:27] = 7 cycles
	#	Write High Time      [21:20] = 3 cycles
	#	Write Low Time       [19:16] = 5 cycles
	#	Read Recovery Time   [6:4] = 6 cycles
	#	Read Time            [3:0] = 10 cycles

	li	t0,0x3835006a	# Settings -> t0
	li	t1,0xb0008230	# PHY Control Register -> t1
	sw	t0,0(t1)	    # Configure PHY

sdram_pup:	

	# Setup for 80 MHz to 100 MHz
	# Set the SDRAM Control Reg to:
	#	LP   = OFF
	#	CL   = 3
	#       RC   = 10
	#       DP2  = 0
	#       RBS  = 1
    #	    BBD2 = 0
	# Set refresh rate to: 1250 cycles


	/****************************************
	* Write SDRAM control in Mem Controler *
	****************************************/

	li	t1,0x0030a100	# Fill t1 with SDRAM control
	li	t3,0xb0008208	# SDRAM Control Reg Addr -> t1
	sw	t1,0(t3)	# Store preferences -> SDRAM Control Reg
	
				# Precharge the SDRAM	
	li	t1,0x00000001	# 0x1 -> t0
	li	t3,0xb0008210	# Precharge Cmd Reg Addr -> t1
	sw	t1,0(t3)	# Do a precharge

	/***************************************
	* Write refresh rate to Mem Controler *
	***************************************/
	
	li	t2,0x000004e2	# Fill t2 with refresh rate
	li	t3,0xb0008200	# SDRAM Refresh Reg Addr -> t1
	sw	t2,0(t3)	# Set refresh rate

	/*********************************************************************
	* Have Mem Controler configure SDRAM to agree with above parameters *
	*********************************************************************/

	# Set the Mode Reg to:
	#	Burst Length = 8
	#	Wrap Type	= 0
	#	Latency Mode	= 3

	li	t0,0x00000033	# t0 <- 0x33 
	li	t1,0xb0008218	# SDRAM Mode Set Reg -> t1
	sw	t0,0(t1)	    # Set Mode Reg (really doesn't matter what this value is)

	# Refer to tech spec info on Mem Controller and NEC
	#  SDRAM part uPD4516821

	li	t0,0x00000033	# t0 <- 0x33
	li	t1,0xa0019800	# You must write to this addr in order to set the Mode reg to 0x33
	sw	t0,0(t1)	# Set Mode Reg

	/**********************************
	* Refresh all SDRAM banks twice  *         
	**********************************/
	
	# Do first refresh of SDRAM

	li	t0,0x00000001	# t0 <- 0x1
	li	t1,0xb0008220	# SDRAM Refresh Cycle Cmd Reg Addr -> t1
	sw	t0,0(t1)	    # Refresh SDRAM

    # Do second refresh of SDRAM
	#  Note: must read value first to clear write back buffer

	lw	t3,0(t1)	# SDRAM Refresh Cycle Cmd Reg -> t3
	li	t0,0x00000002	# t0 <- 0x2
	sw	t0,0(t1)	# Refresh SDRAM


    /* 
        Setup Serial Ice Port
    */

    li      t1, UART_BASE

    li      t0, 0xfffffffe              #Take Uart out of reset
    sw      t0, OFFSET_reset(t1)

    li      t0, 0x00000008              #Turn loopback off, Select system clock
    sw      t0, OFFSET_config(t1)

    li      t0, STATUS_DRDY_INT
    sw      t0, OFFSET_status(t1)

    li      t0, 0x000000e3              #1 stopbit, no parity 8 data bits, ignor cts, ignor dsr, ignor dcd
    sw      t0, OFFSET_channel(t1)

    li      t0, 43                      # Select 115200 Baud
    sw      t0, OFFSET_divisor(t1)

    sw      zero, OFFSET_reset(t1)      # Take out of Tx and Rx Halt

	la	    k0,savearea
	la	    t0,get_word
	sw	    t0,ICE_GWP*4(k0)
	la	    t0,put_word
	sw	    t0,ICE_PWP*4(k0)
	li	    t0,IBUFSIZE
	sw	    t0,ICE_IBS*4(k0)
	li	    t0,REG_MAP
	sw	    t0,ICE_MAP*4(k0)
	li	    t0,SA_VERS
	sw	    t0,ICE_SAV*4(k0)
	li	    t0,ICE_SAHSIZE
	sw	    t0,ICE_SAH*4(k0)
	sw	    zero,ICE_LE*4(k0)

	# enable ints in SR MASK+IEC
	li	    k0,(SR_CU0 | SR_BEV | SR_IEC|UART_INTBIT)
	.set noreorder
	mtc0	k0,C0_SR
    nop
    nop
	.set reorder
	# print banner

    li      a0,0x44434241   # DCBA
    bal     put_word

1:
    b       1b

    .end cpu_init