k4011.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

#if 0 /* echo the input. Useful for debug */
	move	a0,v0
	bal	put_word
	b	ice_loop
#endif
   	# check for SENDA0
	li	k1,SENDA0
	bne	k1,v0,1f

	# It is SENDA0. Execute the code in INSTR_BUFFER and send 
	# the value of register a0.
	# Make sure that the routine ends with a "j ra".
	sw	zero,(s0)
	li	k0,J_RA_INSTR
	sw	k0,4(s0)
	sw	zero,8(s0)
	# Make sure that the writes complete before the jal.
	.set noreorder
	nop
	nop
	nop
	.set reorder
	# Reset s0 to point to start of INSTR_BUFFER.
	li	s0,INSTR_BUFFER
	jal	s0		# execute INSTR_BUFFER
	bal	put_word	# send A0
	b	ice_loop

   1:	# check for RUN_MODE
	li	k1,RUN_MODE
	bne	k1,v0,1f

restore_rfe:
	# It is RUN_MODE. Transfer control to the client.
	# restore regs
	la	k0,SAVEAREA
	lw	AT,ICE_AT*4(k0)
	lw	v0,ICE_V0*4(k0)
	lw	a0,ICE_A0*4(k0)
	lw	a1,ICE_A1*4(k0)
	lw	a2,ICE_A2*4(k0)
	lw	a3,ICE_A3*4(k0)
	lw	t0,ICE_T0*4(k0)
	lw	t1,ICE_T1*4(k0)
	lw	t2,ICE_T2*4(k0)
	lw	t3,ICE_T3*4(k0)
	lw	t4,ICE_T4*4(k0)
	lw	s0,ICE_S0*4(k0)
	lw	ra,ICE_RA*4(k0)
	.set noreorder
	lw	k0,ICE_EPC*4(k0)
	nop
#ifdef R4KEXCEPTIONS
	mtc0	k0,C0_EPC
	nop
	nop
	nop
	eret
	nop
#else
	j	k0		# jump to client
	rfe
#endif
	.set reorder

   1:	# check for SENDSAP
	li	k1,SENDSAP
	bne	k1,v0,1f

	# It is SENDSAP. Send address of SAVEAREA.
	la	a0,SAVEAREA
	or	a0,1		# indicate new format
	bal	put_word
	b	ice_loop

   1:	# else. Not a special word.
	sw	v0,(s0)		# save word in INSTR_BUFFER
	addu	s0,4		# ready for next word
	b	ice_loop
	.end ice_loop

	.set at

/*************************************************************
*  get_cmd()
*	Get one word from the serial interface. The result goes
*	in v0.
*/
	.globl get_cmd
	.ent get_cmd
get_cmd:
	li	k1,UART_BASE
	li	a1,4			# get 4 bytes

	# wait for rxrdy
   3:   lw      k0,UART_RXS(k1)
	and	k0,RXS_RXRDY
        beq     k0,zero,3b

	# get the byte
        lw      k0,UART_RXHR(k1)

	# first byte?
	bne	a1,4,2f			# brif not first byte

	# is the byte a wakeup?
	bne	k0,ATTN,2f		# brif not a wakeup

	# wait for txrdy
   1:   lw      k0,UART_TXS(k1)
	and	k0,TXS_TXRDY
        beq     k0,zero,1b

	# send an ack
	li	k0,ACK
        sw      k0,UART_TXHR(k1)
	b	3b

   2:	sll	v0,8			# move word into position
	or	v0,k0			# merge byte with word
	subu	a1,1			# bytecount--
	bne	a1,zero,3b		# do next byte

	j	ra
	.end get_cmd

/*************************************************************
*  get_word()
*       Get one word from the serial interface. The result goes
*       in v0.
*/
        .globl get_word
        .ent get_word
get_word:
        li      k1,UART_BASE
        li      a1,4

   1:   lw      k0,UART_RXS(k1)
	and	k0,RXS_RXRDY
        beq     k0,zero,1b

        lw      k0,UART_RXHR(k1)
        sll     v0,8
        or      v0,k0
        subu    a1,1
        bne     a1,zero,1b

        j       ra
        .end get_word

/*************************************************************
*  put_word()
*       Put one word to the serial interface. The word to be sent
*       comes from a0.
*/
        .globl put_word
        .ent put_word
put_word:
        li      k1,UART_BASE
        li      a1,4

   1:   lw      k0,UART_TXS(k1)
	and	k0,TXS_TXRDY
        beq     k0,zero,1b

        sw      a0,UART_TXHR(k1)
        srl     a0,8
        subu    a1,1
        bne     a1,zero,1b

        j       ra
        .end put_word

/*************************************************************
* 		End of interrupt-level code		     *
*************************************************************/
	.set at


/*************************************************************
*  cpu_init()
*	This is where the CPU-specific init code lives.
*	This implementation is for the Nitro (4010/11 eval board).
*	This example is designed to use ChanA of the DUART for connection
*	to the IceController.
*/
	.globl cpu_init
	.ent cpu_init
cpu_init:
	# setup the CCC configuration register
	# enable: CMP, IIE, DIE, MUL, MAD, BGE, IPWE(1K), WB
	# Icache: 2 way set assoc, 8K set size
	# Dcache: 2 way set assoc, 8K set size
	# CCC <- 0000 0001 1111 0111 1111 1110 0010 0000
#ifdef R4KEXCEPTIONS
	li	t0, 0x0037fe20		# w/o IIE,DIE
#else
	li	t0, 0x0137fe20		# w/o IIE,DIE
#endif
	.set noreorder
	mtc0	t0, C0_CCC		# load the CP0 configuration register
	.set reorder

	# Initialize the Synchronous DRAM controller
	li 	t0, M_DRAM_CFG
	li 	t1, 0x7033A753
	sw	t1, (t0)

	# set the CAS Latency
        li      t0, M_CL3		# CAS latency = 3
        sw      zero, (t0)

	# set Refresh rate
	li 	t0, M_DRAM_REFRESH
	li 	t1, 0x00000271		# at 40 Mhz 
	sw	t1, (t0)

	# enable scbus bus error detection
	li	t0,M_SCBUS_ST
	li	t1,3
	sw	t1,(t0)

#ifndef USE_NO_INTS
	# enable the RXINTS
        li      t1,UART_BASE
	li	t0,RXC_IE
	sw	t0,UART_RXC(t1)
#endif

	 j	ra
	.end cpu_init


#ifdef RUN_APPLICATION

#define RAM_GENVECT	0x80000080
#define STACKSIZE	(8*1024)
	.comm	stack,STACKSIZE
	.comm   flush_cache_ptr,4

/*************************************************************
*/
	.globl _exit
	.globl cstartup
	.ent cstartup
cstartup:
        # identify CPU and flush both caches
	la	s0,r4010_flush
        or      s0,K1BASE
        li      a0,ICACHEI
        jal     s0
        li      a0,DCACHEI
        jal     s0

#if 1	/* necessary for ROM-resident code */
	# copy the data to RAM
	li	a0,FDATA
	jal	cpdata
#endif

	# note that clrbss must not use a3
	jal	clrbss

	# set the global data pointer
	la	gp,_gp

	# save the address of the cache flush routine
	sw	s0,flush_cache_ptr

	# set sp
	la	sp,stack+STACKSIZE-24

#if 1	/* use the RAM-resident exception vectors */
	# copy exception handler to RAM vector
	la	t1,ehandler
	la	t2,ehandler_end
	li	t3,RAM_GENVECT	
   1:	lw	t0,(t1)
	sw	t0,(t3)
	addu	t1,4
	addu	t3,4
	bne	t1,t2,1b

	# flush the Icache
        li      a0,ICACHE
        jal     flush_cache

	# clear BEV
	.set noreorder
	mfc0	t0,C0_SR
	nop
	and	t0,~SR_BEV
	mtc0	t0,C0_SR
	.set reorder
#endif

 	# call the main C routine
	la	t0,main
	jal	t0
_exit:
	b	_exit
	.end cstartup


/*************************************************************
*  getmachtype()
*	Return the CPU type.
*/
	.globl getmachtype
	.ent getmachtype
getmachtype:
	li	v0,4011
	j	ra
	.end getmachtype


/*************************************************************
*  ehandler:
*	This is the exception handler that gets copied to RAM.
*	If the application uses exceptions, it will use this
*	code to transfer control to the IceKernel for all 
*	non-application exceptions.
*/
	.ent ehandler
ehandler:
	la	k0,gen_vector
	j	k0
ehandler_end:
	.end ehandler

/*************************************************************
*  flush_cache(type)
*	A C-callable routine to flush the caches.
*/
	.globl flush_cache
	.ent flush_cache
flush_cache:
	lw	t0,flush_cache_ptr
	j	t0
	.end flush_cache

#endif /*  RUN_APPLICATION */