c64360.c

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/c64360.c
 * Purpose: Part of C runtime library
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	970304	Start of revision history
 *	980616	Added "case 8" devinit.
 *	980730	Added F_MIPS for Crossview
 *	980730	Fixed the HI reg #.
 */

#ifndef LR64360
#define LR64360
#endif
#include <mon.h>
#include <termio.h>
#include <terms.h>

char *c64360_c0regs[] = {
	"$0",     "$1",  "$2",  "C0_BPC",  
	"$4",   "C0_BDA",   "C0_TAR",    "C0_DCIC",
 	"C0_BADADDR", "C0_BDAM",  "$10",  "C0_BPCM", 
	"C0_SR",      "C0_CAUSE", "C0_EPC",    "C0_PRID",
	"$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
	"$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
	};

char *cellszvals[] = {"64", "60", "56", "52", 0};
char *bufszvals[] = {"4", "8", "16", "32", 0};
char *cbsvals[] = {"2", "4", "-", "-", 0};

RegSpec Scrreg[] = {
	{2,30,"RO",0,cellszvals,0},
	{2,28,"TO",0,cellszvals,0},
	{1,27,"RI",2,0,0},
	{1,26,"TI",2,0,0},
	{1,24,"BM",2,0,0},
	{3,21,"HH",2,0,0},
	{2,19,"CBS",0,cbsvals,0},
	{3,16,"BS",0,bufszvals,0},
	{1,15,"CRCERR",2,0,0},
	{1,14,"SAFE",2,0,0},
	{6,8,"CH",10,0,0},
	{1,6,"BOCERR",2,0,0},
	{1,5,"RWD",2,0,0},
	{1,4,"AWD",2,0,0},
	{3,0,"TAF",10,0,0},
        {0}};

char *l64360bsv[] = {"2","4","8","16",0};


RegSpec l64360biu[] = {
        {1,17,"NOSTR",2,0,0},
        {1,16,"LDSCH",2,0,0},
	{1,15,"BGNT",2,0,0},
	{1,14,"NOPAD",2,0,0},
	{1,13,"RDPRI",2,0,0},
	{1,12,"INTP",2,0,0},
	{1,11,"IS1",2,0,0},
	{1,10,"IS0",2,0,0},
	{2,8,"IBLKSZ",0,l64360bsv,0},
	{1,7,"DS1",2,0,0},
	{1,6,"DS0",2,0,0},
	{2,4,"DBLKSZ",0,l64360bsv,0},
	{1,3,"RAM",2,0,0},
	{1,2,"TAG",2,0,0},
	{1,1,"INV",2,0,0},
	{1,0,"LOCK",2,0,0},
	{0}};

RegRec c64360_reglist[] = {
	{mXpc,0,"PC","pc",14,(F_MIPS|F_CPU)},
	{mXgpr,0,"HI","HI",32,(F_CPU|F_MIPS)},
	{mXgpr,0,"LO","LO",33,(F_CPU|F_MIPS)},
	/* ========== cp0 ========== */
	{mXc0,mips_sr_def,"C0_SR","SR",12,(F_CP0|F_MIPS)},
	{mXc0,mips_cause_def,"C0_CAUSE","CAUSE",13,(F_CP0|F_MIPS)},
	{mXc0,mips_prid_def,"C0_PRID","PRID",15,(F_CP0|F_RO|F_MIPS)},
	{mXc0,0,"C0_EPC","EPC",14,(F_CP0|F_MIPS)},
	{mXc0,0,"C0_BADVA","BADVA",8,(F_CP0|F_MIPS)},
/*--------- end of basic MIPS stuff ------------------------*/
	{mXmem,l64360biu,"M_BIU","BIU",M_BIU,0},
	{mXmem,0,"M_CREDIT","CREDIT",M_CREDIT,F_RO},
	{mXmem,0,"M_CONFIG","CONFIG",M_CONFIG,F_WO},
	{mXmem,0,"M_STALL","STALL",M_STALL,F_WO},
	{mXmem,0,"M_PRPC","PRPC",M_PRPC,(0)},
	{mXmem,0,"M_RXBUFPTR","RXBUFPTR",M_RXBUFPTR,(0|F_RO)},
	{mXmem,0,"M_TXFIFO","TXFIFO",M_TXFIFO,(0|F_WO)},
	{mXmem,0,"M_RXACK","RXACK",M_RXACK,(0|F_WO)},
	{mXmem,0,"M_GPRR","GPRR",M_GPRR,(0|F_WO)},
	{mXmem,Scrreg,"M_SCR","SCR",M_SCR,(0)},
	{mXmem,0,"M_AHI","AHI",M_AHI,(0|F_WO)},
	{mXmem,0,"M_CRC32","CRC32",M_CRC32,(0)},
	{mXmem,0,"M_ASUBR","ASUBR",M_ASUBR,(0|F_WO)},
	{0}};

int c64360_read_iram(), c64360_write_iram();

int p2681();
static struct p2681info tty1dat = {0xa0e00000,3,4};

#ifndef PMCC
a64360init(type) { c64360init(type); }
#endif

c64360init(type)
int type;
{
int i;

switch (type) {
	case 1 : 
		read_target_mem_ptr = c64360_read_iram;
		write_target_mem_ptr = c64360_write_iram;
		break;
	case 2 :
                c0regNames = c64360_c0regs;
                for (i=0;c64360_reglist[i].func;i++) {
                        addRegRec(&c64360_reglist[i]);
                        }
		break;
	case 4 :
#ifdef NVRAM
		nvInfo.gap = 1;
		nvInfo.width = 1;
		nvInfo.nvbase = 0;
		nvInfo.start = 0xa0c00000;
#endif
		break;
	case 8 : 
		addDevice((Addr)&tty1dat,0,p2681,1024,DEFBAUD);
		addDevice((Addr)&tty1dat,1,p2681,1024,DEFBAUD);
		break;
	}
}