r4010cfl.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/r4010cfl.s
 * Purpose: Part of C runtime library
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	970304	Start of revision history
 *	971118	Removed code to skip set if in scrathpad mode
 *	980827	Fixed reorder directives to avoid hazard.
 */

#ifndef LR4010
#define LR4010
#endif
#include <mips.h>

/*************************************************************
*  Flushing the 4010 caches
*
*	To flush the Icache, issue the instruction 0xbc010000.
*	To flush the Dcache, issue the instruction 0xbc020000.
*	To flush both caches, issue the instruction 0xbc030000.
*	To write-back a Dcache line, issue the instruction 0xbc040000
*		specifying offset and base.
*/


/*************************************************************
*  r4010_flush(type,adr)
*	Flush the designated LR4010 cache.
*	Note that this isn't a real subroutine, it just transfers
*	control to the appropriate flush routine.
*/
	.globl r4010_flush
	.ent r4010_flush
r4010_flush:
	bne	a0,ICACHEI,1f
	j	r4010_iflush

1:	bne	a0,ICACHE,1f
	j	r4010_iflush

1:	bne	a0,DCACHE,1f
	j	r4010_dflush

1:	bne	a0,DCACHEI,1f
	j	r4010_dflushi

1:	move	a0,a1
	j	r4010_iflush
	.end r4010_flush

/*************************************************************
*  r4010_iflush()
*	Flush the LR4010 Instruction cache.
*/
	.globl r4010_iflush
	.ent r4010_iflush
r4010_iflush:
	# disable ints
	.set noreorder
	mfc0	t7,C0_SR
	nop
	and	t0,t7,~SR_IEC
	mtc0	t0,C0_SR
	.set reorder

	# switch to Kseg1
	la	t0,1f
	li	t1,K1BASE
	or	t0,t1
	j	t0
1:

#if 0
	# we don't want to flush any sets that have been
	# switched to scratchpad ram mode.

	# read ccc to get current settings
	.set noreorder
	mfc0	t8,C0_CCC
	nop
	.set reorder
	# is isr1 set?
	and	t0,t8,CCC_ISR1
	beq	t0,zero,1f 	# brif not set

	# isr1 is set. so clear ie1
	and	t0,t8,~CCC_IE1
	.set noreorder
	mtc0	t0,C0_CCC
	.set reorder
1:
#endif

	.set noreorder
	flush_icache
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	mtc0	t7,C0_SR	# restore SR

#if 0
	# restore ccc
	mtc0	t8,C0_CCC
#endif
	.set reorder		# 980827

	j	ra
	.end r4010_iflush

/*************************************************************
*  r4010_dflush()
*	Flush the LR4010 Data cache.
*	o disable ints
*	o switch to kseg1
*	o write-back the cache
*	o invalidate the cache
*/
	.globl r4010_dflush
	.ent r4010_dflush
r4010_dflush:
	# disable ints
	.set noreorder
	mfc0	t7,C0_SR
	nop
	and	t0,t7,~SR_IEC
	mtc0	t0,C0_SR
	.set reorder

	# switch to Kseg1
	la	t0,1f
	li	t1,K1BASE
	or	t0,t1
	j	t0
1:

#if 0
	# we don't want to flush any sets that have been
	# switched to scratchpad ram mode.

	# read ccc to get current settings
	.set noreorder
	mfc0	t8,C0_CCC
	nop
	.set reorder
	move	t1,t8
	# is sr0 set?
	and	t0,t8,CCC_SR0
	beq	t0,zero,1f 	# brif not set

	# sr0 is set. so clear de0
	and	t1,~CCC_DE0
1:
	# is sr1 set?
	and	t0,t8,CCC_SR1
	beq	t0,zero,1f 	# brif not set

	# sr1 is set. so clear de1
	and	t1,~CCC_DE1
	.set noreorder
	mtc0	t1,C0_CCC
	.set reorder
1:
#endif

	# first we want to write-back the Dcache
	li	t0,K0BASE
	addu	t1,t0,8192		# 8KB cache

	.set noreorder
1:	
	# WB instruction to write-back the Dcache
	# for some reason the MIPS assembler complains if I unroll the loop
	wb_dcache(0,r_t0)		/* writes 8 words */
	nop
	addu	t0,(8*4)
	bne	t0,t1,1b
	nop

	# now flush the Dcache
	nop
	nop
	flush_dcache
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	nop
	mtc0	t7,C0_SR	# restore SR

#if 0
	# restore ccc
	mtc0	t8,C0_CCC
#endif
	.set reorder		# 980827

	j	ra
	.end r4010_dflush

/*************************************************************
*  r4010_dflushi()
*	Initial Flush of the LR4010 Data cache. No copy-back.
*/
	.globl r4010_dflushi
	.ent r4010_dflushi
r4010_dflushi:
	# disable ints
	.set noreorder
	mfc0	t7,C0_SR
	nop
	and	t0,t7,~SR_IEC
	mtc0	t0,C0_SR
	.set reorder

	# switch to Kseg1
	la	t0,1f
	li	t1,K1BASE
	or	t0,t1
	j	t0
1:

	# now flush the Dcache
	.set noreorder
	flush_dcache
	nop
	nop
	nop
	nop
	nop
	mtc0	t7,C0_SR	# restore SR
	.set reorder
	j	ra
	.end r4010_dflushi