a4102.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/a4102.s
 * Purpose: Part of C runtime library
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	980615	Created from a4101.s
 *	981216	Added ifdef for LE PMON. refillsz = 1.
 *	990303	Added code to make sure that timer0 is disabled. Required
 *		for "init -c".
 *	990317	Updated various values.
 */

#define MR990317	/* use mrally's changes of 990317 */

/* one and only one of these two lines MUST be enabled */
#define BOOT_SDRAM 	/* SDRAM=0 SRAM=0xa1000000 */
/*#define BOOT_SRAM 	/* SRAM=0 SDRAM=0xa1000000 */

/*#define NO_SDRAM	/* don't enable SDRAM at all. Use w BOOT_SRAM */

#ifndef LR4102
#define LR4102
#endif
#include <mips.h>

	.globl a4102init
	.ent a4102init
a4102init:
	beq     a0,zero,1f
	j       c4102init
    1:

 # Setup Bus Unit Chip Selects
 #
 #============ Set up FLASH in addr space assign to CS0 ===================
 #
 #  Note: FACMP0 and FACMP1 are initialized on startup to a 2M space starting
 #  at address 0x1fc00000.   These registers only need to be changed if you
 #  have a boot flash larger than 2 Meg in size.

        li      t1, M_FBUSTA
#ifdef MR990317
	li	t2, 0x00160111		# 990317 was 161111
#else
	li	t2, 0x00161111		# 990317 was 161111
#endif
        sw      t2, (t1)               # Set FBUSTA = 1 turn around time

        li      t1, M_FACFG0
        li      t0, 0x02949517         # Set 8 bit, 11 wait states     
        sw      t0, (t1)               # Store Flash Timing settings

 #============ Initialize random register       ======================

        .set noreorder
        mtc0    zero, C0_RANDOM        # initialize the random register
        nop     
        .set reorder

 #============ Setup SRAM in addr space assign to CS3    ==================

        li      t1, M_FACMP3     # Assign CS3 to SRAM in address range
#ifdef BOOT_SRAM
        li      t0, 0x00010000         # 0x00000000 to 0x0001ffff
#else
        li      t0, 0x00010e00         # 0x0e000000 to 0x0e01ffff
#endif
        sw      t0, (t1)               # Assign CS3 address range

        li      t1, M_FACFG3     
#ifdef MR990317
        li      t0, 0xc2100005         # 990317 Set 32 bit, 2 wait states
#else
        li      t0, 0xc2949507         # Set 32 bit, 3 wait states
#endif
        sw      t0, (t1)               # Store SRAM timing settings
        lw      zero, (t1)

	# Setup Uart and Seven Segment Display assign to CS4

        la      t1, M_FACMP4           # Assign CS4 to UART/7SEG in addr range
        li      t0, 0x00001e00         # 0x1e000000 to 0x1e00ffff
        sw      t0, (t1)               # Set FACMP3 to 0x00001fbf

        la      t1, M_FACFG4
        li      t0, 0x0a50901f         # Set 8 bit, 15 wait states
        sw      t0, (t1)
        lw      zero, (t1)             # Flush Write buffer

        li      t0, 0xf8               # Light a 7
        la      t4, 0xbe000020         # Led port address
        sw      t0, (t4)               # Light it!


 # Setup BBCC System Configuration Register 
 #
 # Initialize Bus Unit interface.  This routine enables all caches.

#ifdef MIPSEB
	li      t1, M_SCR1        
	li      t0, 0x300010db   # Enable Caches + snooping
	sw      t0, (t1)         # Configure SCR1, pg size = 256
#else /* LE needs refill sizes set to 1 */
	li      t1, M_SCR1        
	li      t0, 0x30001093   # Enable Caches + snooping
	sw      t0, (t1)         # Configure SCR1, pg size = 256
#endif
                                

#ifndef NO_SDRAM
 # Initialize SDRAM controller
 #
 # This routine inits the SDRAM controller on the 4102.  It begins by
 # configuring the address range for the SDRAM and all of the timing
 # parameters.  It then waits for 100 usec using the timer0 as a count
 # down.  Finally it issues a precharge to bank 0, 1, 2 & 3 followed by 2
 # refreshes and configures the SDRAM for 1 word burst.

 # The SDRAM controller strobes out a new address with each read request.


	# Set SDRAM clock
        li      t0, M_SCR2        # Set bclkp to run at
                                        # pclk speed
        lw      t2, (t0)                # Read current PLL jumper status
        and     t2, 0x00000010          # Mask off all but the PLL bit
        li      t1, 0x000200a8          # and dclkp to run at
        or      t1, t2                  # bclk or 100MHz
        sw      t1, (t0)                # and enable 4101
                                        # compatibility mode

	# Issue COMMAND INHIBIT by not reading or writing to 
	# DRAM and wait for 100 us

	# 990303 first make sure that timer0 is disabled
	li      t0, M_TMR4001+O_TMODE
	li      t2, 0x00000000          # Disable Timer0 and Timer1
	sw      t2, (t0)                # Store in Register

	li      t0, M_TMR4001+O_TIC0
	li      t1, M_TMR4001+O_TCC0

	li      t2, 0x00000100          # Setup Timer to wait 
					# 100us  0x2710
	sw      t2, (t0)                # Store data
	li      t0, M_TMR4001+O_TMODE
	li      t2, 0x00000011          # Enable Timer0 Disable Timer1
	sw      t2, (t0)                # Store in Register

1:
	lw      t2, (t1)                # Read from Counter
	bne     zero, t2, 1b            # Loop till done

	# Enable SDRAM in addr range 2

	li      t0, M_FACMP2		# Set FACMP2
#ifdef BOOT_SDRAM
	li      t2, 0x07ff0000          # Address range 2 covers 
					# 0x00000000 to
	sw      t2, (t0)                # 0x00ffffff, 16MB Dram
#else
	li      t2, 0x00ff0200          # Address range 2 covers 
					# 0x01000000 to
	sw      t2, (t0)                # 0x01ffffff, 16MB Dram
#endif

	# Set SDRAM Configuration

	li      t0, M_FSDRAM
	li      t2, 0x000d8609          # Set SDRAM to 4 banks, 
					# 15.6 usec refresh
	sw      t2, (t0)                # 8 bit page size, 4 Meg 
					# bank size 

	# Enable SDRAM
	li      t0, M_FACFG2
	li      t1, 0xd0000001          # enable SDRAM 32 bit 
					# wide bus         
	sw      t1, (t0)        

	# Set FSDRAMT timing register

	li      t0, M_FSDRAMT     # Set SDRAM Timing for 
					# Lat = 3 cks
#ifdef MR990317
        li      t2, 0x000057a4          # 990317 tRC = 9 cks, tCL = 3 cks, 
					# tRAS = 6 cks
#else
	li      t2, 0x0000f0aa          # tRC = 2 cks, tCL = 3 cks, 
					# tRAS = 7 cks
#endif
	sw      t2, (t0)                # Set Init Bit so that next 
					# read is a bank 
					# Precharge.  Set for MODE 
					# Register write 
					# on next Write to SDRAM
						
	# Issue a Precharge to each bank of SDRAM
#ifdef BOOT_SDRAM
	li      t1, 0xa0000000          # Execute dummy read to 
					# uncached SDRAM
#else
	li      t1, 0xa2000000          # Execute dummy read to 
					# uncached SDRAM
#endif
	lw      zero, (t1)              # Read Banks in order to 
					# precharge
 
	# Issue 2 Refresh cycles to SDRAM

	li      t0, M_FSDRAM
	li      t2, 0x000d8609          # Set SDRAM Config

	sw      t2, (t0)                # Store in FSDRAM to cause 
					# a refresh
	lw      zero, (t0)              # Flush write buffers
	ori     t0, t0, 0x0             # Flush write buffers

	sw      t2, (t0)                # Store in FSDRAM to cause 
					# a second refresh    
	lw      zero, (t0)              # Flush write buffers
	ori     t0, t0, 0x0             # Flush write buffers

	# Set SDRAM mode register
#ifdef MR990317 /* 990317 */
	li      t0, M_FSDRAMT
	lw	t4,(t0)
	or	t4,0x8000
	sw	t4,(t0)
#endif

#ifdef BOOT_SDRAM
	li      t1, 0xa008c000          # Set SDRAM Mode Reg to 
#else
	li      t1, 0xa208c000          # Set SDRAM Mode Reg to 
#endif

#ifdef MR990317 /* 990317 */
	lb	zero,(t1)
	li      t0, M_FSDRAMT
	and	t4,~0xc000
	sw	t4,(t0)
#else
	sw      zero, (t1)              # Execute SDRAM Mode Reg write
					# by reading from a0006000 
					# uncached
        
	li      t0, M_FSDRAMT     	# Disable Mode Register 
					# Write & Init
	li      t1, 0x000038aa          
	sw      t1, (t0)         
#endif
#endif

#if 0
	# enable int0 for berr signals
	.set noreorder
	mfc0	t0,C0_SR
	nop
	or	t0,(SR_IBIT3|SR_IEC)
	mtc0	t0,C0_SR
	nop		# give it time...
	nop
	nop
	.set reorder
#endif
        li      t0, ~0x40              # Light center bar
        la      t4, 0xbe000020         # Led port address
        sw      t0, (t4)               # Light it!

	# select the correct cache flushing routines
	la	s0,r4001_flush

	j	ra
	.end a4102init