a64364.s

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/a64364.s
 * Purpose: Part of C runtime library
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	980624	Created from a64363.s
 */

#ifndef LR64364
#define LR64364
#endif

#include <mips.h>

	############# ATMizer-II+ (LR64364) #################
	.globl a64364init
	.ent a64364init
a64364init:
	beq	a0,zero,1f
	j	c64364init
    1:
	# setup the CCC configuration register
	# enable: CMP, IIE, DIE, MUL, MAD, IPWE(1K), WB
	# Icache: 2 way set assoc, 4K set size
	# Dcache: 2 way set assoc, 2K set size
	# CCC <- 0000 0001 1111 0011 1011 0110 0010 0000
	li	t0, 0x01f3b600		# without write-back
	.set noreorder
	mtc0	t0, C0_CCC		# load the CP0 configuration register
	.set reorder

	# setup the wait states of local memory page 0, 1, 2 */
    	li	t1,0xf803feee
	li	t2,M_SBCR
	sw	t1,(t2)

	# new...
	# setup the Secondary Clock Control register for SB_CLKO delay
    # with respect to internal system clock
    # This delay is required for proper ASRAM operation
    li	t1,0x00000006
	li	t2,0xb8000810
	sw	t1,(t2)

	# setup the AddrMap Register to direct exceptions
	# to the SDRAM.
	li	t1,(0<<ADRM_EXCMAP_SHFT)
	li	t2,M_APU_AddrMap
	sw	t1,(t2)

	# setup the SDRAM config info
	li	t2, SBC_BASE 		/* Load base address */

	/* Precharge command */
	li	t0, 0x4033b753
	sw	t0, 4(t2)		# control reg

	/* Mode register */
	li	t0, 0x20228530
	sw	t0, 4(t2)		# control reg

	/* Set Mode */
	li	t0, 0x0000eeee
	li	t3, 0xA0818000 # Modified from 0x80810000 by Shree on 06/09/1998
	sw	t0, (t3)

	/* Set Control */
	li	t0, 0x10328530
	sw	t0, 4(t2)		# control reg

	/* Load refresh register */
	li	t0, 0x00000300
	sw	t0, 8(t2)		# refresh reg

	# select the correct cache flushing routines
	la	s0,r4010_flush

	j	ra
	.end a64364init