r4001cfl.s

来自「mips架构的bootloader,99左右的版本 但源代码现在没人更新了」· S 代码 · 共 343 行

/*************************************************************
 * File: lib/r4001cfl.s
 * Purpose: Part of C runtime library
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	970304	Start of revision history
 *	970402	Added the "don't flush locked entries" to set0
 *	970523	Changed all routines to flush 32KB (2048 lines)
 */

/* To flush the Dcache (for example), you must switch the cache into
 * maintenance mode.  You do this by setting the CMODE to the DTEST mode
 * (or ITEST for the Icache).
 * 
 * Once you have the cache in TEST mode, all kseg0 accesses go to the cache
 * tag ram rather than memory.  This means that you must be sure that no
 * other code is going to interrupt you, and that your cache flush code is
 * executing from kseg1.  Now you perform store-word of zero to each of the
 * lines of the cache.  This sets the entire tag ram to zero.  This will
 * clear both the lock bit and the 4 valid bits for each line.  So if you
 * had anything locked in the cache before the flush, you certainly don't
 * afterward.
 * 
 * Note that you must have DCEN when you flush the DCACHE, and you must
 * have ICEN, IS1EN *and* DCEN enabled when you flush the Icache.  This
 * means that you are flushing both sets of the Icache at the same time.
 */


#include <mips.h>
#ifdef LR4001

/*************************************************************
*  r4001_flush(type,adr)
*	Flush the designated LR4001 cache.
*	Note that this isn't a real subroutine, it just transfers
*	control to the appropriate flush routine.
*/
	.globl r4001_flush
	.ent r4001_flush
r4001_flush:
	bne	a0,ICACHEI,1f
	j	r4001_iflushi

1:	bne	a0,ICACHE,1f
	j	r4001_iflush

1:	bne	a0,DCACHE,1f
	j	r4001_dflush

1:	bne	a0,DCACHEI,1f
	j	r4001_dflush

1:	move	a0,a1
	j	r4001_iaflush
	.end r4001_flush


/*************************************************************
*  r4001_iflushi()
*	Initial flush of the LR4001 Instruction cache.
*/
	.globl r4001_iflushi
	.ent r4001_iflushi
r4001_iflushi:
	# disable ints
	.set noreorder
	mfc0	t7,C0_SR
	nop
	and	t0,t7,~SR_IEC
	mtc0	t0,C0_SR
	.set reorder

	# switch to Kseg1
	la	t0,1f
	li	t1,K1BASE
	or	t0,t1
	j	t0

1:	
	lw	t8,M_CFG4001

	# set 0
	li	t2,K0BASE
	addu	t4,t2,2048*16	# can have up to 32KB per set

	and	t0,t8,~(CFG_CMODEMASK|CFG_DCEN|CFG_IS1EN)
	or	t0,(CFG_ICEN)
	# DCEN has to be on for all software tests     JFK 12/7/95
	or	t0,(CFG_DCEN)
	or	t0,CFG_CMODE_ITEST
	sw	t0,M_CFG4001
	lw	t0,M_CFG4001	# wb flush
	addu	t0,1		# wb flush

1:	sw	zero,(t2)
	addu	t2,16
	bne	t4,t2,1b

	# set 1
	li	t2,K0BASE
	addu	t4,t2,2048*16	# can have up to 32KB per set

	and	t0,t8,~(CFG_CMODEMASK|CFG_DCEN)
	or	t0,(CFG_ICEN|CFG_IS1EN)
	# DCEN has to be on for all software tests     JFK 12/7/95
	or	t0,(CFG_DCEN)
	or	t0,CFG_CMODE_ITEST
	sw	t0,M_CFG4001
	lw	t0,M_CFG4001	# wb flush
	addu	t0,1		# nop

1:	sw	zero,(t2)
	addu	t2,16
	bne	t4,t2,1b
	.set noreorder
	nop
	nop
	nop
	sw	t8,M_CFG4001	# restore CFGREG
	lw	t0,M_CFG4001	# wb flush
	nop
	addu	t0,1		# wb flush
	mtc0	t7,C0_SR	# restore SR
	.set reorder
	j	ra
	.end r4001_iflushi

/*************************************************************
*  r4001_iflush()
*	Flush the non-locked entries in the LR4001 Instruction cache.
*/
	.globl r4001_iflush
	.ent r4001_iflush
r4001_iflush:
	# disable ints
	.set noreorder
	mfc0	t7,C0_SR
	nop
	and	t0,t7,~SR_IEC
	mtc0	t0,C0_SR
	.set reorder

	# switch to Kseg1
	la	t0,1f
	li	t1,K1BASE
	or	t0,t1
	j	t0

1:	
	lw	t8,M_CFG4001

	# set 0
	li	t2,K0BASE
	addu	t4,t2,2048*16	# can have up to 32KB per set

	and	t0,t8,~(CFG_CMODEMASK|CFG_DCEN|CFG_IS1EN)
	or	t0,(CFG_ICEN)
	# DCEN has to be on for all software tests     JFK 12/7/95
	or	t0,(CFG_DCEN)
	or	t0,CFG_CMODE_ITEST
	sw	t0,M_CFG4001
	lw	t0,M_CFG4001	# wb flush
	addu	t0,1		# nop

#if 1 /* only flush non-locked entries */
   1:	lw	t0,(t2)
	sll	t0,27
	bltz	t0,2f
	sw	zero,(t2)
   2:	addu	t2,16
	bne	t4,t2,1b
#else
   1:	sw	zero,(t2)
	addu	t2,16
	bne	t4,t2,1b
#endif

	# set 1
	li	t2,K0BASE
	addu	t4,t2,2048*16	# can have up to 32KB per set

	and	t0,t8,~(CFG_CMODEMASK|CFG_DCEN)
	or	t0,(CFG_ICEN|CFG_IS1EN)
	# DCEN has to be on for all software tests     JFK 12/7/95
	or	t0,(CFG_DCEN)
	or	t0,CFG_CMODE_ITEST
	sw	t0,M_CFG4001
	lw	t0,M_CFG4001	# wb flush
	addu	t0,1		# nop

#if 0 /* only flush non-locked entries */
   1:	lw	t0,(t2)
	sll	t0,27
	bltz	t0,2f
	sw	zero,(t2)
   2:	addu	t2,16
	bne	t4,t2,1b
#else
   1:	sw	zero,(t2)
	addu	t2,16
	bne	t4,t2,1b
#endif

	.set noreorder
	nop
	nop
	nop
	sw	t8,M_CFG4001	# restore CFGREG
	lw	t0,M_CFG4001	# wb flush
	nop
	addu	t0,1		# wb flush
	mtc0	t7,C0_SR	# restore SR
	.set reorder
	j	ra
	.end r4001_iflush

/*************************************************************
*  r4001_dflush()
*	Flush the LR4001 Data cache.
*/
	.globl r4001_dflush
	.ent r4001_dflush
r4001_dflush:
	# disable ints
	.set noreorder
	mfc0	t7,C0_SR
	nop
	and	t0,t7,~SR_IEC
	mtc0	t0,C0_SR
	.set reorder

	# switch to Kseg1
	la	t0,1f
	li	t1,K1BASE
	or	t0,t1
	j	t0

1:	li	t2,K0BASE
	addu	t4,t2,2048*16	# can have up to 32KB per set

	lw	t8,M_CFG4001
	and	t0,t8,~(CFG_CMODEMASK|CFG_ICEN|CFG_IS1EN)
	or	t0,(CFG_DCEN)
	or	t0,CFG_CMODE_DTEST
	sw	t0,M_CFG4001
	lw	t0,M_CFG4001	# wb flush
	addu	t0,1		# nop

1:	sw	zero,(t2)
	addu	t2,16
	bne	t4,t2,1b

	.set noreorder
	nop
	nop
	nop
	sw	t8,M_CFG4001	# restore CFGREG
	lw	t0,M_CFG4001	# wb flush
	nop
	addu	t0,1		# nop
	mtc0	t7,C0_SR	# restore SR
	.set reorder
	j	ra
	.end r4001_dflush

/*************************************************************
*  r4001_iaflush(addr)
*	Flush a single entry in the LR4001 Instruction cache.
*/
	.globl r4001_iaflush
	.ent r4001_iaflush
r4001_iaflush:
	# a0=addr
	# return if the address is non cacheable
	srl	t0,a0,29
	bne	t0,5,1f
	j	ra

   1:	# word align the address
	li	t0,~3
	and	a0,t0

	# disable ints
	.set noreorder
	mfc0	t7,C0_SR
	nop
	and	t0,t7,~SR_IEC
	mtc0	t0,C0_SR
	.set reorder

	# switch to Kseg1
	la	t0,1f
	li	t1,K1BASE
	or	t0,t1
	j	t0

1:	lw	t8,M_CFG4001

	# set 0
	and	t0,t8,~(CFG_CMODEMASK|CFG_DCEN|CFG_IS1EN)
	or	t0,(CFG_ICEN)
	# DCEN has to be on for all software tests     JFK 12/7/95
	or	t0,(CFG_DCEN)
	or	t0,CFG_CMODE_ITEST
	sw	t0,M_CFG4001
	lw	t0,M_CFG4001	# wb flush
	addu	t0,1		# nop

	sw	zero,(a0)

	# set 1
	and	t0,t8,~(CFG_CMODEMASK|CFG_DCEN)
	or	t0,(CFG_ICEN|CFG_IS1EN)
	or	t0,CFG_CMODE_ITEST
	sw	t0,M_CFG4001
	lw	t0,M_CFG4001	# wb flush
	addu	t0,1		# nop

	sw	zero,(a0)

	.set noreorder
	nop
	nop
	nop
	sw	t8,M_CFG4001	# restore CFGREG
	lw	t0,M_CFG4001	# wb flush
	nop
	addu	t0,1		# nop
	nop
	mtc0	t7,C0_SR	# restore SR
	.set reorder
	j	ra
	.end r4001_iaflush

#else /* some versions of BSO tools don't like empty files */
	.globl r4001_dummy
	.ent r4001_dummy
r4001_dummy:
	j	ra
	.end r4001_dummy
#endif /* LR4001 */