c65066.c

mips架构的bootloader,99左右的版本 但源代码现在没人更新了

/*************************************************************
 * File: lib/c65066.c
 * Purpose: Init code for 65066 DCAM-111
 * Author: Phil Bunce ([e-mail])
 * Revision History:
 *	990212	Created from c90084.c
 */

/* This version is for the hw emulation model. So it uses the old DCAM-103
 * type memory controller rather than the fbus controller that the real chip
 * will use.
 */

#ifndef L65066
#define L65066
#endif

#include "mips.h"
#include <termio.h>
#include <terms.h>
#include <pmon.h>

#define inw(a)		(*((volatile Ulong *)(a)))
#define outw(a,v)	(*((volatile Ulong *)(a))=(v))
#define outh(a,v)	(*((volatile Ushort *)(a))=(v))

/* 4102 cpu 32-bit timer */
#define TMRI	(M_TMR4001+O_TIC1)  /* initial value */
#define TMRC	(M_TMR4001+O_TCC1)  /* current value */
#define TMODE	(M_TMR4001+O_TMODE) /* control */
#define TSTAT	(M_TMR4001+O_TSTAT) /* status */

static RegSpec scr1[] = {
	{1,31,"MMU",2,0,0},
	{1,30,"WBEN",2,0,0},
	{1,29,"DSNPEN",2,0,0},
	{1,28,"ISNPEN",2,0,0},
	{1,19,"CPC3EN",2,0,0},
	{1,18,"CPC2EN",2,0,0},
	{1,17,"CPC1EN",2,0,0},
	{1,16,"CPC0EN",2,0,0},
	{1,13,"DBERR",2,0,0},
	{3,10,"PGSZ",10,0,0},
	{2,8,"CMODE",10,0,0},
	{1,7,"RDPRI",2,0,0},
	{2,5,"DSIZE",10,0,0},
	{1,4,"DCEN",2,0,0},
	{2,2,"ISIZE",10,0,0},
	{1,1,"IS1",2,0,0},
	{1,0,"ICEN",2,0,0},
	{0}};

static RegSpec scr2[] = {
	{1,21,"TMRIE1",2,0,0},
	{1,20,"TMRIE0",2,0,0},
	{1,19,"MRR",2,0,0},
	{1,17,"4101C",2,0,0},
	{1,16,"MDUSATE",2,0,0},
	{1,15,"MDUSATI",2,0,0},
	{1,14,"FDBSTOP",2,0,0},
	{4,7,"CLKDB",2,0,0},
	{2,5,"CLKDD",2,0,0},
	{1,4,"CLKSEL",2,0,0},
	{1,3,"CLKPLLE",2,0,0},
	{1,2,"CLKST",2,0,0},
	{2,0,"CLKDC",2,0,0},
	{0}};

static RegSpec TmrMode4102[] = {
	{1,13,"D1",2,0,0},
	{1,12,"S1",2,0,0},
	{1,11,"I1",2,0,0},
	{1,10,"M1",2,0,0},
	{1,9,"P1",2,0,0},
	{1,8,"E1",2,0,0},
	{1,5,"D0",2,0,0},
	{1,4,"S0",2,0,0},
	{1,3,"I0",2,0,0},
	{1,2,"M0",2,0,0},
	{1,1,"P0",2,0,0},
	{1,0,"E0",2,0,0},
	{0}};

static RegSpec TmrStat4102[] = {
	{1,3,"IN1",2,0,0},
	{1,2,"IE1",2,0,0},
	{1,1,"IN0",2,0,0},
	{1,0,"IE0",2,0,0},
	{0}};

static RegRec reglist[] = {
	{mXpc,0,"PC","pc",14,(F_CPU|F_MIPS)},
	{mXgpr,0,"HI","HI",32,(F_CPU|F_MIPS)},
	{mXgpr,0,"LO","LO",33,(F_CPU|F_MIPS)},
	{mXc0,mips_sr_def,"C0_SR","SR",12,(F_CP0|F_MIPS)},
	{mXc0,mips_cause_def,"C0_CAUSE","CAUSE",13,(F_CP0|F_MIPS)},
	{mXc0,0,"C0_EPC","EPC",14,(F_CP0|F_MIPS)},
	{mXc0,0,"C0_BADVA","BADVA",8,(F_CP0|F_MIPS)},
	{mXc0,mips_prid_def,"C0_PRID","PRID",15,(F_CP0|F_RO|F_MIPS)},
	{mXmem,scr1,"M_SCR1","SCR1",M_SCR1},
	{mXmem,scr2,"M_SCR2","SCR2",M_SCR2},
	{mXmem,0,"M_TIC0","TIC0",M_TMR4001+O_TIC0},
	{mXmem,0,"M_TCC0","TCC0",M_TMR4001+O_TCC0},
	{mXmem,0,"M_TIC1","TIC1",M_TMR4001+O_TIC1},
	{mXmem,0,"M_TCC1","TCC1",M_TMR4001+O_TCC1},
	{mXmem,TmrStat4102,"M_TSTAT","TSTAT",M_TMR4001+O_TSTAT},
	{mXmem,TmrMode4102,"M_TMODE","TMODE",M_TMR4001+O_TMODE},
#ifdef USE_FBUS
	{mXmem,0,"M_FACFG0","FACFG0",M_FACFG0},
	{mXmem,0,"M_FACFG1","FACFG1",M_FACFG1},
	{mXmem,0,"M_FACFG2","FACFG2",M_FACFG2},
	{mXmem,0,"M_FACFG3","FACFG3",M_FACFG3},
	{mXmem,0,"M_FACFG4","FACFG4",M_FACFG4},
	{mXmem,0,"M_FACFG5","FACFG5",M_FACFG5},
	{mXmem,0,"M_FBUSTA","FBUSTA",M_FBUSTA},
	{mXmem,0,"M_FACMP0","FACMP0",M_FACMP0},
	{mXmem,0,"M_FACMP1","FACMP1",M_FACMP1},
	{mXmem,0,"M_FACMP2","FACMP2",M_FACMP2},
	{mXmem,0,"M_FACMP3","FACMP3",M_FACMP3},
	{mXmem,0,"M_FACMP4","FACMP4",M_FACMP4},
	{mXmem,0,"M_FACMP5","FACMP5",M_FACMP5},
	{mXmem,0,"M_FBUSCMP","FBUSCMP",M_FBUSCMP},
	{mXmem,0,"M_FBUSAC","FBUSAC",M_FBUSAC},
	{mXmem,0,"M_FBUSCFG","FBUSCFG",M_FBUSCFG},
	{mXmem,0,"M_FBURST","FBURST",M_FBURST},
	{mXmem,0,"M_FSFLASH","FSFLASH",M_FSFLASH},
	{mXmem,0,"M_FSDRAM","FSDRAM",M_FSDRAM},
	{mXmem,0,"M_FDRAMT","FDRAMT",M_FDRAMT},
	{mXmem,0,"M_FSDRAMT","FSDRAMT",M_FSDRAMT},
	{mXmem,0,"M_FSDRAM2","FSDRAM2",M_FSDRAM2},
	{mXmem,0,"M_FGPCFG","FGPCFG",M_FGPCFG},
	{mXmem,0,"M_FGPOUTPUT","FGPOUTPUT",M_FGPOUTPUT},
	{mXmem,0,"M_FGPINPUT","FGPINPUT",M_FGPINPUT},
#endif
	{0}};

static char *c0_regs[] = {
	"$0",     "$1",  "$2",  "$3",  
	"$4",   "$5",  "$6", "$7",
 	"C0_BADADDR", "C0_COUNT", "$10",  "$11", 
	"C0_SR",      "C0_CAUSE", "C0_EPC",    "C0_PRID",
	"C0_CONFIG",  "$17", "$18",    "$19", 
	"$20",    "$21",  "$22",       "C0_ROTATE",
	"C0_CMASK", "$25", "$26", "$27", 
	"$28", "$29", "$30", "$31"
	};

int cache_cmd400x();
extern Optdesc cache_opts400x[];

static CmdRec cmds[] = {
	{"cache",cache_opts400x,cache_cmd400x},
	{0}};

#if 0
static int measureFreq();
#endif

extern int dcache_size,icache_size,cache_line_size;

static int setbp_target(),brkInstall(),brkRemove();

int p90084();
int iceport();
static struct iceportinfo iceportdat = {0xbfff0200};

/*************************************************************
*  c65066init(type)
*/
c65066init(type)
int type;
{
Ulong saved_sr;
int n,cf,i;

switch (type) {
	case 1 :
		break;
	case 2 :
		c0regNames = c0_regs;
		for (i=0;reglist[i].func;i++) addRegRec(&reglist[i]);
		for (i=0;cmds[i].name;i++) addCmdRec(&cmds[i]);
		icache_size = 4*1024;
		dcache_size = 4*1024;
		cache_line_size = 16;
		brkInstall_ptr = brkInstall;
		brkRemove_ptr = brkRemove;
		setbp_target_ptr = setbp_target;
		break;
	case 3 :  /* hostInit(3) extra memory */
		break;
	case 4 : /* hostInit(4) nvInfo */
#ifdef NVRAM
		nvInfo.start = 0xbfc00000;
		nvInfo.width = 4; 	
		nvInfo.gap   = 1; 
		nvInfo.nvbase  = 0; 
#endif
		break;
	case 5 : /* hostInit(5) adjust refresh rate... */
		break;
	case 6 : 
#if 0
		/* 970927 If the iceport has no clock (no txrdy) the
		"init -c" command won't work. */
		if (inw(0xbfff0208)&1)
			addDevice((Addr)&iceportdat,0,iceport,1024,B9600);
#endif
		break;
	case 8 :
		addDevice((Addr)l0084_sio,0,p90084,1024,DEFBAUD);
		addDevice((Addr)l0084_sio,1,p90084,1024,DEFBAUD);
		addDevice((Addr)l0084_sio,2,p90084,1024,DEFBAUD);
		break;
	}
}


#if 0
/*************************************************************
*  measureFreq()
*
* The scheme I use is to the number of cpu cycles that were
* executed while waiting for a fixed time to elapse.
* 
* To wait a fixed time I transmit two nulls at 9600 via the UART.
* 
* To measure the cpu clocks, I use timer1 inside the cpu.
* 
*/
static measureFreq()
{
Ulong cpu;
static measure_4102();

#ifdef CLKFREQ
return CLKFREQ; /* 981107 */
#endif

/* throw away the 1st measurement */
measure_4102();
cpu = measure_4102()*10;
return ((cpu/109)+17)/100;
/*
 * Add 17  and divide by * 100 for rounding.
 */
}


static measure_4102()
{
Ulong cpu,dummy,tmode;
char *p;

/* make sure that the tx is completely empty */
while (!(inb(LSR_16550)&TEMT_16550)) ;

/* start timer at zero */
tmode = inw(TMODE)&~TMODE_MASK1;
outw(TMODE,tmode); /* stop timer */
outw(TMRI,0xffffffff);
outw(TMODE,tmode|TMODE_E1);  /* start */

while (!(inb(LSR_16550)&THRE_16550)) ;
outb(THR_16550,0);
while (!(inb(LSR_16550)&THRE_16550)) ;
outb(THR_16550,0);

/* make sure that the tx is completely empty */
while (!(inb(LSR_16550)&TEMT_16550)) ;

/* read CPU timer */
cpu = 0xffffffff-inw(TMRC);
outw(TMODE,tmode); /* stop timer */
return(cpu/2); /* div */
}
#endif

/*************************************************************
*  static int setbp_target(n,type,addr,addr2,value)
*       type: 1=bpc 2=bda 3=itemp 4=sstep 5=nonrt
*       returns bp number, or -1 on error.
*	addr2 and value are only used for BPTYPE_DATA.
*	In the case of BPTYPE_DATA the access type (r/w) is encoded
*	in the 2nd nibble of 'type';
*/
static int setbp_target(n,type,addr,addr2,value)
int n,type;
Ulong addr,addr2,value;
{
int i,method,atype,code;
long mask; /* must be signed */
 
if (verbose) fprintf(dfp,"setbp_target(%d,%d,%08x,%08x,%08x)\n",
		n,type,addr,addr2,value);

atype = type>>4;
type &= 0xf;
code = 0;
if (type == BPTYPE_NONRT) {
        printf("Warning: This breakpoint requires non real-time execution.\n");
        }
else if (type == BPTYPE_PC || type == BPTYPE_ITMP || type == BPTYPE_TRACE) {
        if (is_writeable_target(addr)) {
		if (verbose) fprintf(dfp,"is writeable\n");
		method = BRK_METHOD_RAM;
		}
        else if (IS_K0SEG(addr) && ilockReq400x(addr)) {
		if (verbose) fprintf(dfp,"ilock avail\n");
		method = BRK_METHOD_ROM;
		}
        else {
                printf("%08x: can't set bpt\n",addr);
                return(0-BP_E_ERR);
                }
        }
else if (type == BPTYPE_DATA) {
	return(0-BP_E_ERR);
	}

if (n == -1) {
        for (i=0;i<MAX_BPT;i++) if (brkList[i].type == 0) break;
        if (i >= MAX_BPT) {
                printf("Fatal error: out of bpts\n");
                return(0-BP_E_ERR);
                }
        n = i;
        }
if (n < 0 || n >= MAX_BPT) {
        printf("%d: bad bpt number\n",n);
        return(0-BP_E_ERR);
        }
brkList[n].type = type;
brkList[n].addr = addr;
brkList[n].method = method;
brkList[n].mask = mask;
brkList[n].isset = 0;
return((code<<16)|n);
}

/*************************************************************
*  static int brkInstall(type)
*	type=1 install regular+temp bpts
*	type=2 install trace bpts
*/
static int brkInstall(type)
int type;
{
int i,flag;
Ulong tag,vmask,addr,cfg;

if (verbose) fprintf(dfp,"brkInstall(%d)\n",type);

for (i=0;i<MAX_BPT;i++) {
	/* first discard the entries we aren't going to handle */
	if (brkList[i].type==0) continue;
	if (type == 1 && brkList[i].type == BPTYPE_TRACE) continue;
	if (type == 2 && brkList[i].type != BPTYPE_TRACE) continue;

	addr = brkList[i].addr;
	switch (brkList[i].method) {
	    case BRK_METHOD_RAM :
		if (verbose) fprintf(dfp,"installing ram bpt at %08x\n",addr);
		if (addr&1) {
			addr &= ~1;
			brkList[i].val = read_target(XT_MEM,addr,2);
			outh(addr,TINY_BPT_CODE);
			}
		else {
			brkList[i].val = read_target(XT_MEM,addr,4);
			outw(addr,BPT_CODE);
			}
		iflush_needed = 1;
		brkList[i].isset = 1;
		break;

	    case BRK_METHOD_ROM :
		if (verbose) fprintf(dfp,"installing rom bpt at %08x\n",addr);
		cfg = read_target(XT_MEM,M_CFG4001,4);
		if ((cfg&CFG_ISIZEMASK) == CFG_ISIZE_8) { /* 970709 */
			/* handle the irefillsz=8 case */
			wrrombp4101(addr);
			}
		else {
			vmask = 1<<((addr>>2)&3);
			writeLockedBpt400x(addr,vmask);
			}
		brkList[i].isset = 1;
		break;

	    default : 
		printf("%d: error bad method\n",brkList[i].method);
		return(-1);
	    }
	}
}

/*************************************************************
*  static int brkRemove(epc)
*	returns type: 0=none 1=bpc 2=bda 3=itemp 4=sstep
*/
static int brkRemove(epc)
Ulong epc;
{
int i,type;
Ulong addr;

type = 0;
for (i=0;i<MAX_BPT;i++) {
	/* first discard the entries we aren't going to handle */
	if (brkList[i].type==0) continue;
	if (brkList[i].isset==0) continue;

	if (epc == brkList[i].addr) type = brkList[i].type;
	switch (brkList[i].method) {
	    case BRK_METHOD_RAM :
		addr = brkList[i].addr;
		if (addr&1) outh(addr&~1,brkList[i].val);
		else outw(addr,brkList[i].val);
		iflush_needed = 1;
		break;

	    case BRK_METHOD_ROM :
		writeCache400x(0,ICACHETAG,brkList[i].addr,0);
		break;

	    }
	if (brkList[i].type == BPTYPE_ITMP) brkList[i].type = 0;
	if (brkList[i].type == BPTYPE_TRACE) brkList[i].type = 0;
	}
return(type);
}