编码器的设计.txt

protel电路板设计

library ieee;
use ieee.std_logic_1164.all;
entity ch4_1_2 is
  port(a:in std_logic_vector(7 downto 0);
       en:in std_logic;
       y:out std_logic_vector(2 downto 0));
end ch4_1_2;
architecture endec_behave of ch4_1_2 is
signal sel:std_logic_vector(8 downto 0);
begin
      sel<=en & a;
   with sel select
   y<="000"when"100000001",
      "001"when"100000010",
      "010"when"100000100",
      "011"when"100001000",
      "100"when"100010000",
      "101"when"100100000",
      "110"when"101000000",
      "111"when"110000010",
      "000"when others;
end endec_behave;