译码器的设计.txt

protel电路板设计

library ieee;
use ieee.std_logic_1164.all;
entity dec is
     port(
          sel:in std_logic_vector(2 downto 0);
          en:in std_logic;
          y:out std_logic_vector(7 downto 0)
         );
end dec;
architecture dec_arch of dec is
begin
    process(sel,en)
   begin
     y<="11111111";
     if(en='1')then
     case sel is  
          when"000"=>y(0)<='0';
          when"001"=>y(1)<='0'; 
          when"010"=>y(2)<='0';
          when"011"=>y(3)<='0'; 
          when"100"=>y(4)<='0'; 
          when"101"=>y(5)<='0'; 
          when"110"=>y(6)<='0'; 
          when"111"=>y(7)<='0'; 
          when others=>null;
     end case;
     end if;
    end process;
end dec_arch;