project_0.plg

upsd34xx系列单片机keil环境中的开发例程

Current project is: 'project'

AHDL2BLF  ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'project'

  Processing equations..............

  Module parsing complete. Building logic network...

  Creating Berkeley PLA file project.tt1...

Module 'project' processing complete.

Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 2 seconds

BLIFOPT  Open-ABEL Optimizer 
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file project.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file project.xrf... 
Writing Open-ABEL (PLA) file project.tt2...

BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds

DIOFFT  Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: project.tt2.
Output file: project.tt3.


DIOFFT complete. - Time 0 seconds

AHDL2BLF  ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'project'

  Processing equations..............

  Module parsing complete. Building logic network...

  Creating Berkeley PLA file project.tt1...

Module 'project' processing complete.

Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds

AHDL2BLF  ABEL-HDL Processor
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Module: 'project'

  Processing equations..............

  Module parsing complete. Building logic network...

  Creating Berkeley PLA file project.tt1...

Module 'project' processing complete.

Using backup JHD file.
AHDL2BLF complete - 0 errors, 0 warnings. Time: 1 seconds

BLIFOPT  Open-ABEL Optimizer 
U.C. Berkeley, SIS Ver. 1.0, modified by Data I/O Corp.
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Reading Open-ABEL (PLA) file project.tt1...
Performing 'bypin choose' optimization...
Shortening signal names...
Writing signal name cross reference file project.xrf... 
Writing Open-ABEL (PLA) file project.tt2...

BLIFOPT complete - 0 errors, 0 warnings. Time: 1 seconds

DIOFFT  Flip-Flop Transformation program
PSDabel-CPLD 6.20 Copyright 1983-1994 Data I/O Corp. All Rights Reserved.
Input file: project.tt2.
Output file: project.tt3.


DIOFFT complete. - Time 0 seconds

PSD Fitter - Logic Synthesis and Device Fitting
PSDsoft Express 8.30 Copyright (C) 1993-2004 STMicroelectronics, Inc.  All Rights Reserved.
PROJECT    : project                          DATE : 02/23/2005
DEVICE     : uPSD3434E                        TIME : 15:38:08
FIT OPTION : Keep Current
DESCRIPTION: Starting Template for New DK3400 Projects
Main Flash is 
located in Code Space: FS0 = 0000h, FS1..FS7 = Paged at 8000h
Boot 
Flash is located in Data Space: BS0..BS3 = 8000h to FFFFh
SRAM 
and CSIOP is located in Data Space: RS0 = 0000h CSIOP = 7F

  >> PSD Fitter complete - Successful Fitting
  >> View fitter report for detail

PSDsoft ends.