📄 mcf523x_etpu_struc.h
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vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ } B; } CDTROSR_A; union { /* ETPU_B Data Transfer Overflow Status */ vuint32_t R; struct { vuint32_t DTROS31:1; /* Channel 31 Data Transfer Overflow Status */ vuint32_t DTROS30:1; /* Channel 30 Data Transfer Overflow Status */ vuint32_t DTROS29:1; /* Channel 29 Data Transfer Overflow Status */ vuint32_t DTROS28:1; /* Channel 28 Data Transfer Overflow Status */ vuint32_t DTROS27:1; /* Channel 27 Data Transfer Overflow Status */ vuint32_t DTROS26:1; /* Channel 26 Data Transfer Overflow Status */ vuint32_t DTROS25:1; /* Channel 25 Data Transfer Overflow Status */ vuint32_t DTROS24:1; /* Channel 24 Data Transfer Overflow Status */ vuint32_t DTROS23:1; /* Channel 23 Data Transfer Overflow Status */ vuint32_t DTROS22:1; /* Channel 22 Data Transfer Overflow Status */ vuint32_t DTROS21:1; /* Channel 21 Data Transfer Overflow Status */ vuint32_t DTROS20:1; /* Channel 20 Data Transfer Overflow Status */ vuint32_t DTROS19:1; /* Channel 19 Data Transfer Overflow Status */ vuint32_t DTROS18:1; /* Channel 18 Data Transfer Overflow Status */ vuint32_t DTROS17:1; /* Channel 17 Data Transfer Overflow Status */ vuint32_t DTROS16:1; /* Channel 16 Data Transfer Overflow Status */ vuint32_t DTROS15:1; /* Channel 15 Data Transfer Overflow Status */ vuint32_t DTROS14:1; /* Channel 14 Data Transfer Overflow Status */ vuint32_t DTROS13:1; /* Channel 13 Data Transfer Overflow Status */ vuint32_t DTROS12:1; /* Channel 12 Data Transfer Overflow Status */ vuint32_t DTROS11:1; /* Channel 11 Data Transfer Overflow Status */ vuint32_t DTROS10:1; /* Channel 10 Data Transfer Overflow Status */ vuint32_t DTROS9:1; /* Channel 9 Data Transfer Overflow Status */ vuint32_t DTROS8:1; /* Channel 8 Data Transfer Overflow Status */ vuint32_t DTROS7:1; /* Channel 7 Data Transfer Overflow Status */ vuint32_t DTROS6:1; /* Channel 6 Data Transfer Overflow Status */ vuint32_t DTROS5:1; /* Channel 5 Data Transfer Overflow Status */ vuint32_t DTROS4:1; /* Channel 4 Data Transfer Overflow Status */ vuint32_t DTROS3:1; /* Channel 3 Data Transfer Overflow Status */ vuint32_t DTROS2:1; /* Channel 2 Data Transfer Overflow Status */ vuint32_t DTROS1:1; /* Channel 1 Data Transfer Overflow Status */ vuint32_t DTROS0:1; /* Channel 0 Data Transfer Overflow Status */ } B; } CDTROSR_B; uint32_t etpu_reserved15[2]; union { /* ETPU_A Channel Interruput Enable */ vuint32_t R; struct { vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ } B; } CIER_A; union { /* ETPU_B Channel Interruput Enable */ vuint32_t R; struct { vuint32_t CIE31:1; /* Channel 31 Interruput Enable */ vuint32_t CIE30:1; /* Channel 30 Interruput Enable */ vuint32_t CIE29:1; /* Channel 29 Interruput Enable */ vuint32_t CIE28:1; /* Channel 28 Interruput Enable */ vuint32_t CIE27:1; /* Channel 27 Interruput Enable */ vuint32_t CIE26:1; /* Channel 26 Interruput Enable */ vuint32_t CIE25:1; /* Channel 25 Interruput Enable */ vuint32_t CIE24:1; /* Channel 24 Interruput Enable */ vuint32_t CIE23:1; /* Channel 23 Interruput Enable */ vuint32_t CIE22:1; /* Channel 22 Interruput Enable */ vuint32_t CIE21:1; /* Channel 21 Interruput Enable */ vuint32_t CIE20:1; /* Channel 20 Interruput Enable */ vuint32_t CIE19:1; /* Channel 19 Interruput Enable */ vuint32_t CIE18:1; /* Channel 18 Interruput Enable */ vuint32_t CIE17:1; /* Channel 17 Interruput Enable */ vuint32_t CIE16:1; /* Channel 16 Interruput Enable */ vuint32_t CIE15:1; /* Channel 15 Interruput Enable */ vuint32_t CIE14:1; /* Channel 14 Interruput Enable */ vuint32_t CIE13:1; /* Channel 13 Interruput Enable */ vuint32_t CIE12:1; /* Channel 12 Interruput Enable */ vuint32_t CIE11:1; /* Channel 11 Interruput Enable */ vuint32_t CIE10:1; /* Channel 10 Interruput Enable */ vuint32_t CIE9:1; /* Channel 9 Interruput Enable */ vuint32_t CIE8:1; /* Channel 8 Interruput Enable */ vuint32_t CIE7:1; /* Channel 7 Interruput Enable */ vuint32_t CIE6:1; /* Channel 6 Interruput Enable */ vuint32_t CIE5:1; /* Channel 5 Interruput Enable */ vuint32_t CIE4:1; /* Channel 4 Interruput Enable */ vuint32_t CIE3:1; /* Channel 3 Interruput Enable */ vuint32_t CIE2:1; /* Channel 2 Interruput Enable */ vuint32_t CIE1:1; /* Channel 1 Interruput Enable */ vuint32_t CIE0:1; /* Channel 0 Interruput Enable */ } B; } CIER_B; uint32_t etpu_reserved17[2]; union { /* ETPU_A Channel Data Transfer Request Enable */ vuint32_t R; struct { vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ } B; } CDTRER_A; union { /* ETPU_B Channel Data Transfer Request Enable */ vuint32_t R; struct { vuint32_t DTRE31:1; /* Channel 31 Data Transfer Request Enable */ vuint32_t DTRE30:1; /* Channel 30 Data Transfer Request Enable */ vuint32_t DTRE29:1; /* Channel 29 Data Transfer Request Enable */ vuint32_t DTRE28:1; /* Channel 28 Data Transfer Request Enable */ vuint32_t DTRE27:1; /* Channel 27 Data Transfer Request Enable */ vuint32_t DTRE26:1; /* Channel 26 Data Transfer Request Enable */ vuint32_t DTRE25:1; /* Channel 25 Data Transfer Request Enable */ vuint32_t DTRE24:1; /* Channel 24 Data Transfer Request Enable */ vuint32_t DTRE23:1; /* Channel 23 Data Transfer Request Enable */ vuint32_t DTRE22:1; /* Channel 22 Data Transfer Request Enable */ vuint32_t DTRE21:1; /* Channel 21 Data Transfer Request Enable */ vuint32_t DTRE20:1; /* Channel 20 Data Transfer Request Enable */ vuint32_t DTRE19:1; /* Channel 19 Data Transfer Request Enable */ vuint32_t DTRE18:1; /* Channel 18 Data Transfer Request Enable */ vuint32_t DTRE17:1; /* Channel 17 Data Transfer Request Enable */ vuint32_t DTRE16:1; /* Channel 16 Data Transfer Request Enable */ vuint32_t DTRE15:1; /* Channel 15 Data Transfer Request Enable */ vuint32_t DTRE14:1; /* Channel 14 Data Transfer Request Enable */ vuint32_t DTRE13:1; /* Channel 13 Data Transfer Request Enable */ vuint32_t DTRE12:1; /* Channel 12 Data Transfer Request Enable */ vuint32_t DTRE11:1; /* Channel 11 Data Transfer Request Enable */ vuint32_t DTRE10:1; /* Channel 10 Data Transfer Request Enable */ vuint32_t DTRE9:1; /* Channel 9 Data Transfer Request Enable */ vuint32_t DTRE8:1; /* Channel 8 Data Transfer Request Enable */ vuint32_t DTRE7:1; /* Channel 7 Data Transfer Request Enable */ vuint32_t DTRE6:1; /* Channel 6 Data Transfer Request Enable */ vuint32_t DTRE5:1; /* Channel 5 Data Transfer Request Enable */ vuint32_t DTRE4:1; /* Channel 4 Data Transfer Request Enable */ vuint32_t DTRE3:1; /* Channel 3 Data Transfer Request Enable */ vuint32_t DTRE2:1; /* Channel 2 Data Transfer Request Enable */ vuint32_t DTRE1:1; /* Channel 1 Data Transfer Request Enable */ vuint32_t DTRE0:1; /* Channel 0 Data Transfer Request Enable */ } B; } CDTRER_B; uint32_t etpu_reserved20[10]; union { /* ETPU_A Channel Pending Service Status */ vuint32_t R; struct { vuint32_t SR31:1; /* Channel 31 Pending Service Status */ vuint32_t SR30:1; /* Channel 30 Pending Service Status */ vuint32_t SR29:1; /* Channel 29 Pending Service Status */ vuint32_t SR28:1; /* Channel 28 Pending Service Status */ vuint32_t SR27:1; /* Channel 27 Pending Service Status */ vuint32_t SR26:1; /* Channel 26 Pending Service Status */ vuint32_t SR25:1; /* Channel 25 Pending Service Status */ vuint32_t SR24:1; /* Channel 24 Pending Service Status */ vuint32_t SR23:1; /* Channel 23 Pending Service Status */ vuint32_t SR22:1; /* Channel 22 Pending Service Status */ vuint32_t SR21:1; /* Channel 21 Pending Service Status */ vuint32_t SR20:1; /* Channel 20 Pending Service Status */ vuint32_t SR19:1; /* Channel 19 Pending Service Status */ vuint32_t SR18:1; /* Channel 18 Pending Service Status */ vuint32_t SR17:1; /* Channel 17 Pending Service Status */ vuint32_t SR16:1; /* Channel 16 Pending Service Status */ vuint32_t SR15:1; /* Channel 15 Pending Service Status */ vuint32_t SR14:1; /* Channel 14 Pending Service Status */⌨️ 快捷键说明
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