start.s

不包含识别算法

/* start.s,  the boot file */

#define SRAM0base 	0x20000000
#define SRAM1base 	0x20010000
#define FLASHBase 	0xffc00000

#define	MBARBase	__MBAR
#define	MBAR2Base	__MBAR2

.global _start

.extern main_init

/*****************************************************************************/

.section .romvec 

/*
 *	Vector table. This is used for initial platform startup.
 *	These vectors are to catch any un-intended traps.
 */

_vectors:

.long	0x00000000, _start
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault

.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault

.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault

.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault, _fault
.long	_fault, _fault, _fault, _fault, _fault, _fault, _fault




/*
 *   ***************************************************
 *	The very last vector position is stolen to use as a version
 *	number for this boot code :-)
 *   ***************************************************
 */

.text

/**********************************************************************/
/*
 *	This is the initial start up entry point.
 */

_start:

	nop				/* Filler */
	move.w	#0x2700, %sr		/* All interrupts off */

	move.l	#_vectors, %a0		/* Note VBR can't be read */
	movec   %a0, %VBR

/*	jsr	disableCache 
	moveq.l	#0x00000000, %d0	
	movec	%d0, %cacr
	movec	%d0, %ACR0
	movec	%d0, %ACR1
*/

	/* invalidate and disable cache */
	move.l	#0x01000000, %d0		/* Invalidate cache cmd */
	movec	%d0, %CACR			/* Invalidate cache */
	move.l	#0, %d0
	movec	%d0, %ACR0
	movec	%d0, %ACR1

	/* Initialize SRAMBAR */
	move.l	#SRAM0base+1, %d0;		/* locate SRAM, validate it! */
	movec	%a0, %RAMBAR0		/* Note: bit 0 is Validate */
	move.l	#SRAM0base+1, %d0;		/* locate SRAM, validate it! */
	movec	%a0, %RAMBAR1		/* Note: bit 0 is Validate */

	/*
	 *	Set MBAR1 and MBAR2, just incase they are not set.
	 */
	move.l  #MBARBase+1, %a0
	movec   %a0, %MBAR			/* Map MBAR region */
	subq.l  #1, %a0				/* Get MBAR address in a0 */

	move.l  #MBAR2Base+1, %a1
	movec   %a1, #3086	/* ? */		/* Map MBAR2 region */
	subq.l  #1, %a1				/* Get MBAR2 address in a1 */

	/*
	 *	Disable the PLL firstly. (Who knows what state it is
	 *	in here!).
	 */
	move.l  0x180(%a1), %d0			/* Get current PLL value */
	and.l   #0xfffffffe, %d0		/* PLL bypass first */
	move.l  %d0, 0x180(%a1)			/* Set PLL register */
	nop

	/* 11.2896MHz Xtal, mcf5249 core running at 140MHz*/
/*	move.l	#0x01af6837,%d0;			
	move.l	%d0, 0x180(%a1);		
 */
	/*
	 *	Set initial clock frequency. This assumes M5249C3 board
	 *	is fitted with 11.2896MHz crystal. It will program the
	 *	PLL for 140MHz. Lets go fast :-)
	 */
	move.l  #0x125a40f0, %d0		/* Set for 140MHz */
	move.l  %d0, 0x180(%a1)			/* Set PLL register */
	or.l    #0x1, %d0
	move.l  %d0, 0x180(%a1)			/* Set PLL register */

WaitPllReady:
	move.l	0x180(%a1),%d0;  */
	and.l	#0x80000000,%d0;
	beq	WaitPllReady;			/* wait for PLL to lock */


	/* Initialise CS0 */
	move.l	#FLASHBase>>16, %d0;
	move.l	%d0, 0x80(%a0);	/*CSAR*/	/* locate ROM */
	move.l	#0x001F0001,%d0;			/* block size 2 MB, validate */
	move.l	%d0, 0x84(%a0);	/*CSMR*/
	move.l	#0x0980,%d0;			/* port size 16 bit, auto ack. */
	move.l	%d0, 0x88(%a0);	/*CSCR*/


	/* Initialise SDRAM */
	move.l	#0x82090000, %d0;
	move.l	%d0,0x100(%a0);		/* Setup the SDRAM DCR0A register */
	move.l	#0x30002220,%d0;
	move.l	%d0,0x108(%a0);		/* Setup the SDRAM DACR0A register */
	move.l	#0x007c0001,%d0;
	move.l	%d0,0x10c(%a0);		/* Setup the DMR0A register */



	move.l	#___SP_INIT, %sp; 
	
	move.w	#0x2000, %sr;		/* enable interrupts */

	jsr	main_init		/* jump to main C routine */

	/*
	 *	Should never get here!
	 */
panic:
	jmp	panic

/***************************************************************************/

/*
 *	Local fault routine. Shouldn't never get here. If we ever do then
 *	the boot up process has gone badly wrong. Enter the serial port
 *	download state (blinking LEDs so operator knows something is up).
 *
 *	It is possible that the stack pointer is bad, so we will set it
 *	back to a sane value here too.
 */

_fault:

	move.l	#___SP_INIT, %sp	/* Reset stack to local SRAM */
	jmp	_start				/* Should never get here */