📄 mcf5249.h
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#define MCF5249_UART_UMR2_CM_NORMAL (0x00)
#define MCF5249_UART_UMR2_CM_ECHO (0x40)
#define MCF5249_UART_UMR2_CM_LOCAL_LOOP (0x80)
#define MCF5249_UART_UMR2_CM_REMOTE_LOOP (0xC0)
#define MCF5249_UART_UMR2_TXRTS (0x20)
#define MCF5249_UART_UMR2_TXCTS (0x10)
#define MCF5249_UART_UMR2_STOP_BITS_1 (0x07)
#define MCF5249_UART_UMR2_STOP_BITS_15 (0x08)
#define MCF5249_UART_UMR2_STOP_BITS_2 (0x0F)
#define MCF5249_UART_UMR2_STOP_BITS(a) ((a)&0x0f)
#define MCF5249_UART_USR_RB (0x80)
#define MCF5249_UART_USR_FE (0x40)
#define MCF5249_UART_USR_PE (0x20)
#define MCF5249_UART_USR_OE (0x10)
#define MCF5249_UART_USR_TXEMP (0x08)
#define MCF5249_UART_USR_TXRDY (0x04)
#define MCF5249_UART_USR_FFULL (0x02)
#define MCF5249_UART_USR_RXRDY (0x01)
#define MCF5249_UART_UCSR_RCS(a) (((a)&0x0f)<<4)
#define MCF5249_UART_UCSR_TCS(a) ((a)&0x0f)
#define MCF5249_UART_UCR_NONE (0x00)
#define MCF5249_UART_UCR_STOP_BREAK (0x70)
#define MCF5249_UART_UCR_START_BREAK (0x60)
#define MCF5249_UART_UCR_RESET_BKCHGINT (0x50)
#define MCF5249_UART_UCR_RESET_ERROR (0x40)
#define MCF5249_UART_UCR_RESET_TX (0x30)
#define MCF5249_UART_UCR_RESET_RX (0x20)
#define MCF5249_UART_UCR_RESET_MR (0x10)
#define MCF5249_UART_UCR_TX_DISABLED (0x08)
#define MCF5249_UART_UCR_TX_ENABLED (0x04)
#define MCF5249_UART_UCR_RX_DISABLED (0x02)
#define MCF5249_UART_UCR_RX_ENABLED (0x01)
#define MCF5249_UART_UCCR_COS (0x10)
#define MCF5249_UART_UCCR_CTS (0x01)
#define MCF5249_UART_UACR_BRG (0x80)
#define MCF5249_UART_UACR_CTMS_TIMER (0x60)
#define MCF5249_UART_UACR_IEC (0x01)
#define MCF5249_UART_UISR_COS (0x80)
#define MCF5249_UART_UISR_DB (0x04)
#define MCF5249_UART_UISR_RXRDY (0x02)
#define MCF5249_UART_UISR_TXRDY (0x01)
#define MCF5249_UART_UIMR_COS (0x80)
#define MCF5249_UART_UIMR_DB (0x04)
#define MCF5249_UART_UIMR_FFULL (0x02)
#define MCF5249_UART_UIMR_TXRDY (0x01)
/**********************************************************************
*
* SDRAM Controller Module Registers Description
*
***********************************************************************/
#define MCF5249_DRAMC_DCR (*(vuint16 *)(void *)(&__MBAR[0x100]))
#define MCF5249_DRAMC_DACR0 (*(vuint32 *)(void *)(&__MBAR[0x108]))
#define MCF5249_DRAMC_DMR0 (*(vuint32 *)(void *)(&__MBAR[0x10C]))
#define MCF5249_DRAMC_DACR1 (*(vuint32 *)(void *)(&__MBAR[0x110]))
#define MCF5249_DRAMC_DMR1 (*(vuint32 *)(void *)(&__MBAR[0x114]))
/* Controls used by both Synchronous and Asynchronous DRAM */
#define MCF5249_DRAMC_DCR_SO (0x8000)
#define MCF5249_DRAMC_DCR_NAM (0x2000)
#define MCF5249_DRAMC_DCR_RC(a) ((a)&0x01FF)
#define MCF5249_DRAMC_DACR_BASE(a) ((a)&0xFFFC0000)
#define MCF5249_DRAMC_DACR_RE (0x00008000)
#define MCF5249_DRAMC_DACR_PS_32 (0x00000000)
#define MCF5249_DRAMC_DACR_PS_8 (0x00000010)
#define MCF5249_DRAMC_DACR_PS_16 (0x00000020)
#define MCF5249_DRAMC_DCMR_MASK_4G (0xFFFC0000)
#define MCF5249_DRAMC_DCMR_MASK_2G (0x7FFC0000)
#define MCF5249_DRAMC_DCMR_MASK_1G (0x3FFC0000)
#define MCF5249_DRAMC_DCMR_MASK_1024M (0x3FFC0000)
#define MCF5249_DRAMC_DCMR_MASK_512M (0x1FFC0000)
#define MCF5249_DRAMC_DCMR_MASK_256M (0x0FFC0000)
#define MCF5249_DRAMC_DCMR_MASK_128M (0x07FC0000)
#define MCF5249_DRAMC_DCMR_MASK_64M (0x03FC0000)
#define MCF5249_DRAMC_DCMR_MASK_32M (0x01FC0000)
#define MCF5249_DRAMC_DCMR_MASK_16M (0x00FC0000)
#define MCF5249_DRAMC_DCMR_MASK_8M (0x007C0000)
#define MCF5249_DRAMC_DCMR_MASK_4M (0x003C0000)
#define MCF5249_DRAMC_DCMR_MASK_2M (0x001C0000)
#define MCF5249_DRAMC_DCMR_MASK_1M (0x000C0000)
#define MCF5249_DRAMC_DCMR_MASK_1024K (0x00040000)
#define MCF5249_DRAMC_DCMR_MASK_512K (0x00000000)
#define MCF5249_DRAMC_DCMR_WP (0x00000100)
#define MCF5249_DRAMC_DCMR_CPU (0x00000040)
#define MCF5249_DRAMC_DCMR_AM (0x00000020)
#define MCF5249_DRAMC_DCMR_SC (0x00000010)
#define MCF5249_DRAMC_DCMR_SD (0x00000008)
#define MCF5249_DRAMC_DCMR_UC (0x00000004)
#define MCF5249_DRAMC_DCMR_UD (0x00000002)
#define MCF5249_DRAMC_DCMR_V (0x00000001)
/* Controls used only by Asynchronous DRAM*/
#define MCF5249_DRAMC_DCR_RRA_2 (0x0000)
#define MCF5249_DRAMC_DCR_RRA_3 (0x0800)
#define MCF5249_DRAMC_DCR_RRA_4 (0x1000)
#define MCF5249_DRAMC_DCR_RRA_5 (0x1800)
#define MCF5249_DRAMC_DCR_RRP_1 (0x0000)
#define MCF5249_DRAMC_DCR_RRP_2 (0x0200)
#define MCF5249_DRAMC_DCR_RRP_3 (0x0400)
#define MCF5249_DRAMC_DCR_RRP_4 (0x0600)
#define MCF5249_DRAMC_DACR_CAS_1 (0x00000000)
#define MCF5249_DRAMC_DACR_CAS_2 (0x00001000)
#define MCF5249_DRAMC_DACR_CAS_3 (0x00002000)
#define MCF5249_DRAMC_DACR_CAS_4 (0x00003000)
#define MCF5249_DRAMC_DACR_RP_1 (0x00000000)
#define MCF5249_DRAMC_DACR_RP_2 (0x00000400)
#define MCF5249_DRAMC_DACR_RP_3 (0x00000800)
#define MCF5249_DRAMC_DACR_RP_4 (0x00000C00)
#define MCF5249_DRAMC_DACR_RNCN (0x00000200)
#define MCF5249_DRAMC_DACR_RCD_1 (0x00000000)
#define MCF5249_DRAMC_DACR_RCD_2 (0x00000100)
#define MCF5249_DRAMC_DACR_EDO (0x00000040)
#define MCF5249_DRAMC_DACR_PM_OFF (0x00000000)
#define MCF5249_DRAMC_DACR_PM_BURST (0x00000004)
#define MCF5249_DRAMC_DACR_PM_ON (0x0000000C)
/* Controls used only by Synchronous DRAM */
#define MCF5249_DRAMC_DCR_COC (0x1000) /* Command on Clock Enable */
#define MCF5249_DRAMC_DCR_IS (0x0800) /* Initiate Self Refresh Command */
#define MCF5249_DRAMC_DCR_RTIM_3 (0x0000) /* 3 Clocks Between REF and ACTV Cmds */
#define MCF5249_DRAMC_DCR_RTIM_6 (0x0200) /* 6 Clocks Between REF and ACTV Cmds */
#define MCF5249_DRAMC_DCR_RTIM_9 (0x0400) /* 9 Clocks Between REF and ACTV Cmds */
#define MCF5249_DRAMC_DACR_CASL_1 (0x00000000) /* 1 Clock From CAS to Data */
#define MCF5249_DRAMC_DACR_CASL_2 (0x00001000) /* 2 Clock From CAS to Data */
#define MCF5249_DRAMC_DACR_CASL_3 (0x00002000) /* 3 Clock From CAS to Data */
#define MCF5249_DRAMC_DACR_CBM(a) (((a)&0x00000007)<<8) /* Command and Bank Mux */
#define MCF5249_DRAMC_DACR_IMRS (0x00000040) /* Initiate Mode Register Set Cmd */
#define MCF5249_DRAMC_DACR_IP (0x00000008) /* Initiate Precharge All Command */
#define MCF5249_DRAMC_DACR_PM (0x00000004) /* Continuous Page Mode */
/**********************************************************************
*
* Timer Module Registers Description
*
***********************************************************************/
#define MCF5249_TIMER0_TMR (*(vuint16 *)(void *)(&__MBAR[0x140]))
#define MCF5249_TIMER0_TRR (*(vuint16 *)(void *)(&__MBAR[0x144]))
#define MCF5249_TIMER0_TCR (*(vuint16 *)(void *)(&__MBAR[0x148]))
#define MCF5249_TIMER0_TCN (*(vuint16 *)(void *)(&__MBAR[0x14C]))
#define MCF5249_TIMER0_TER (*(vuint8 *)(void *)(&__MBAR[0x151]))
#define MCF5249_TIMER1_TMR (*(vuint16 *)(void *)(&__MBAR[0x180]))
#define MCF5249_TIMER1_TRR (*(vuint16 *)(void *)(&__MBAR[0x184]))
#define MCF5249_TIMER1_TCR (*(vuint16 *)(void *)(&__MBAR[0x188]))
#define MCF5249_TIMER1_TCN (*(vuint16 *)(void *)(&__MBAR[0x18C]))
#define MCF5249_TIMER1_TER (*(vuint8 *)(void *)(&__MBAR[0x191]))
/* some special macros */
#define MCF5249_TIMER_TMR(NUM) (*(vuint16 *)(void *)(&__MBAR[0x140+(NUM * 0x40)]))
#define MCF5249_TIMER_TRR(NUM) (*(vuint16 *)(void *)(&__MBAR[0x144+(NUM * 0x40)]))
#define MCF5249_TIMER_TCR(NUM) (*(vuint16 *)(void *)(&__MBAR[0x148+(NUM * 0x40)]))
#define MCF5249_TIMER_TCN(NUM) (*(vuint16 *)(void *)(&__MBAR[0x14C+(NUM * 0x40)]))
#define MCF5249_TIMER_TER(NUM) (*(vuint8 *)(void *)(&__MBAR[0x151+(NUM * 0x40)]))
/* Bit level definitions and macros */
#define MCF5249_TIMER_TMR_PS(a) (((a)&0x00FF)<<8)
#define MCF5249_TIMER_TMR_CE_ANY (0x00C0)
#define MCF5249_TIMER_TMR_CE_RISE (0x0080)
#define MCF5249_TIMER_TMR_CE_FALL (0x0040)
#define MCF5249_TIMER_TMR_CE_NONE (0x0000)
#define MCF5249_TIMER_TMR_OM (0x0020)
#define MCF5249_TIMER_TMR_ORI (0x0010)
#define MCF5249_TIMER_TMR_FRR (0x0008)
#define MCF5249_TIMER_TMR_CLK_TIN (0x0006)
#define MCF5249_TIMER_TMR_CLK_DIV16 (0x0004)
#define MCF5249_TIMER_TMR_CLK_MSCLK (0x0002)
#define MCF5249_TIMER_TMR_CLK_STOP (0x0000)
#define MCF5249_TIMER_TMR_RST (0x0001)
#define MCF5249_TIMER_TER_REF (0x02)
#define MCF5249_TIMER_TER_CAP (0x01)
/**********************************************************************
*
* Audio interface Registers Description
*
***********************************************************************/
#define MCF5249_AUDIO_IIS1_CFG (*(vuint32 *)(void *)(&__MBAR2[0x010]))
#define MCF5249_AUDIO_IIS2_CFG (*(vuint32 *)(void *)(&__MBAR2[0x014]))
#define MCF5249_AUDIO_IIS3_CFG (*(vuint32 *)(void *)(&__MBAR2[0x018]))
#define MCF5249_AUDIO_IIS4_CFG (*(vuint32 *)(void *)(&__MBAR2[0x01C]))
#define MCF5249_AUDIO_EBU_CFG (*(vuint32 *)(void *)(&__MBAR2[0x020]))
#define MCF5249_AUDIO_EBU_RCV_C_CH_1 (*(vuint32 *)(void *)(&__MBAR2[0x024]))
#define MCF5249_AUDIO_EBU_TX_C_CH_1 (*(vuint32 *)(void *)(&__MBAR2[0x028]))
#define MCF5249_AUDIO_EBU_TX_C_CH_2 (*(vuint32 *)(void *)(&__MBAR2[0x02C]))
#define MCF5249_AUDIO_DATA_IN_CONTROL (*(vuint16 *)(void *)(&__MBAR2[0x032]))
#define MCF5249_AUDIO_PDIR1_L (*(vuint32 *)(void *)(&__MBAR2[0x034]))
#define MCF5249_AUDIO_PDIR3_L (*(vuint32 *)(void *)(&__MBAR2[0x044]))
#define MCF5249_AUDIO_PDIR1_R (*(vuint32 *)(void *)(&__MBAR2[0x054]))
#define MCF5249_AUDIO_PDIR3_R (*(vuint32 *)(void *)(&__MBAR2[0x064]))
#define MCF5249_AUDIO_PDOR1_L (*(vuint32 *)(void *)(&__MBAR2[0x034]))
#define MCF5249_AUDIO_PDOR1_R (*(vuint32 *)(void *)(&__MBAR2[0x044]))
#define MCF5249_AUDIO_PDOR2_L (*(vuint32 *)(void *)(&__MBAR2[0x054]))
#define MCF5249_AUDIO_PDOR2_R (*(vuint32 *)(void *)(&__MBAR2[0x064]))
#define MCF5249_AUDIO_PDOR3 (*(vuint32 *)(void *)(&__MBAR2[0x074]))
#define MCF5249_AUDIO_PDIR (*(vuint32 *)(void *)(&__MBAR2[0x074]))
#define MCF5249_AUDIO_U_CHANNEL_XMIT (*(vuint32 *)(void *)(&__MBAR2[0x084]))
#define MCF5249_AUDIO_U_CHANNEL_RCV (*(vuint32 *)(void *)(&__MBAR2[0x088]))
#define MCF5249_AUDIO_Q_CHANNEL_RCV (*(vuint32 *)(void *)(&__MBAR2[0x08C]))
#define MCF5249_AUDIO_CD_TEXT_CONTROL (*(vuint8 *)(void *)(&__MBAR2[0x093]))
#define MCF5249_AUDIO_INTERRUPT_EN (*(vuint32 *)(void *)(&__MBAR2[0x094]))
#define MCF5249_AUDIO_INTERRUPT_CLEAR (*(vuint32 *)(void *)(&__MBAR2[0x098]))
#define MCF5249_AUDIO_INTERRUPT_STAT (*(vuint32 *)(void *)(&__MBAR2[0x098]))
#define MCF5249_AUDIO_DMA_CONFIG (*(vuint8 *)(void *)(&__MBAR2[0x09F]))
#define MCF5249_AUDIO_PHASE_CONFIG (*(vuint8 *)(void *)(&__MBAR2[0x0A3]))
#define MCF5249_AUDIO_XTRIM (*(vuint16 *)(void *)(&__MBAR2[0x0A6]))
#define MCF5249_AUDIO_FREQ_MEAS (*(vuint32 *)(void *)(&__MBAR2[0x0A8]))
#define MCF5249_AUDIO_BLOCK_CONTROL (*(vuint16 *)(void *)(&__MBAR2[0x0CA]))
#define MCF5249_AUDIO_GLOB (*(vuint16 *)(void *)(&__MBAR2[0x0CE]))
#define MCF5249_AUDIO_EBU2_CONFIG (*(vuint32 *)(void *)(&__MBAR2[0x0D0]))
#define MCF5249_AUDIO_EBU2_RCV_C_CNL_1 (*(vuint32 *)(void *)(&__MBAR2[0x0D4]))
#define MCF5249_AUDIO_U2_CHANNEL_RCV (*(vuint32 *)(void *)(&__MBAR2[0x0D8]))
#define MCF5249_AUDIO_Q2_CHANNEL_RCV (*(vuint32 *)(void *)(&__MBAR2[0x0DC]))
/**********************************************************************
*
* ADC Module Registers Description
*
***********************************************************************/
#define MCF5249_ADC_ADCONFIG (*(vuint16 *)(void *)(&__MBAR2[0x402]))
#define MCF5249_ADC_ADVALUE (*(vuint16 *)(void *)(&__MBAR2[0x406]))
/**********************************************************************
*
* Flash Media Module Registers Description
*
***********************************************************************/
#define MCF5249_FLASHMEDIA_CONFIG (*(vuint32 *)(void *)(&__MBAR2[0x460]))
#define MCF5249_FLASHMEDIA_CMD1 (*(vuint32 *)(void *)(&__MBAR2[0x464]))
#define MCF5249_FLASHMEDIA_CMD2 (*(vuint32 *)(void *)(&__MBAR2[0x468]))
#define MCF5249_FLASHMEDIA_DATA1 (*(vuint32 *)(void *)(&__MBAR2[0x46C]))
#define MCF5249_FLASHMEDIA_DATA2 (*(vuint32 *)(void *)(&__MBAR2[0x470]))
#define MCF5249_FLASHMEDIA_STATUS (*(vuint32 *)(void *)(&__MBAR2[0x474]))
#define MCF5249_FLASHMEDIA_INT_EN (*(vuint32 *)(void *)(&__MBAR2[0x478]))
#define MCF5249_FLASHMEDIA_INT_STAT (*(vuint32 *)(void *)(&__MBAR2[0x47C]))
#define MCF5249_FLASHMEDIA_INT_CLEAR (*(vuint32 *)(void *)(&__MBAR2[0x47C]))
/***********************************************************************/
#define MCF5249_IDE_CONFIG1 (*(vuint32 *)(void *)(&__MBAR2[0x18c])) /* IDE configuration register 1 */
#define MCF5249_IDE_CONFIG2 (*(vuint32 *)(void *)(&__MBAR2[0x190])) /* IDE configuration register 2 */
/********************************************************************/
#endif /* _CPU_MCF5249_H */
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