mcf5249.h

不包含识别算法

#define MCF5249_MBAR2_LS4		(0x00000010)
#define MCF5249_MBAR2_LS3		(0x00000008)
#define MCF5249_MBAR2_LS2		(0x00000004)
#define MCF5249_MBAR2_LS1		(0x00000002)
#define MCF5249_MBAR2_V			(0x00000001)

#define MCF5249_SIM_ICR_AVEC		(0x80)    
#define MCF5249_SIM_ICR_IL(a)		(((a)&0x07)<<2)   
#define MCF5249_SIM_ICR_IP_00		(0x00)
#define MCF5249_SIM_ICR_IP_01		(0x01)
#define MCF5249_SIM_ICR_IP_10		(0x02)
#define MCF5249_SIM_ICR_IP_11		(0x03)

#define MCF5249_SIM_IPR_DMA3		(0x00020000)
#define MCF5249_SIM_IPR_DMA2		(0x00010000)
#define MCF5249_SIM_IPR_DMA1		(0x00008000)
#define MCF5249_SIM_IPR_DMA0		(0x00004000)
#define MCF5249_SIM_IPR_UART1		(0x00002000)
#define MCF5249_SIM_IPR_UART0		(0x00001000)
#define MCF5249_SIM_IPR_MBUS		(0x00000800)
#define MCF5249_SIM_IPR_TIMER1		(0x00000400)
#define MCF5249_SIM_IPR_TIMER0		(0x00000200)
#define MCF5249_SIM_IPR_SWT		(0x00000100)
#define MCF5249_SIM_IPR_EINT7		(0x00000080)
#define MCF5249_SIM_IPR_EINT6		(0x00000040)
#define MCF5249_SIM_IPR_EINT5		(0x00000020)
#define MCF5249_SIM_IPR_EINT4		(0x00000010)
#define MCF5249_SIM_IPR_EINT3		(0x00000008)
#define MCF5249_SIM_IPR_EINT2		(0x00000004)
#define MCF5249_SIM_IPR_EINT1		(0x00000002)

#define MCF5249_SIM_IMR_DMA3		(0x00020000)
#define MCF5249_SIM_IMR_DMA2		(0x00010000)
#define MCF5249_SIM_IMR_DMA1		(0x00008000)
#define MCF5249_SIM_IMR_DMA0		(0x00004000)
#define MCF5249_SIM_IMR_UART1		(0x00002000)
#define MCF5249_SIM_IMR_UART0		(0x00001000)
#define MCF5249_SIM_IMR_MBUS		(0x00000800)
#define MCF5249_SIM_IMR_TIMER1		(0x00000400)
#define MCF5249_SIM_IMR_TIMER0		(0x00000200)
#define MCF5249_SIM_IMR_SWT		(0x00000100)
#define MCF5249_SIM_IMR_EINT7		(0x00000080)
#define MCF5249_SIM_IMR_EINT6		(0x00000040)
#define MCF5249_SIM_IMR_EINT5		(0x00000020)
#define MCF5249_SIM_IMR_EINT4		(0x00000010)
#define MCF5249_SIM_IMR_EINT3		(0x00000008)
#define MCF5249_SIM_IMR_EINT2		(0x00000004)
#define MCF5249_SIM_IMR_EINT1		(0x00000002)

#define MCF5249_SIM_AVCR_AVEC7		(0x80)		
#define MCF5249_SIM_AVCR_AVEC6		(0x40)		
#define MCF5249_SIM_AVCR_AVEC5		(0x20)		
#define MCF5249_SIM_AVCR_AVEC4		(0x10)		
#define MCF5249_SIM_AVCR_AVEC3		(0x08)		
#define MCF5249_SIM_AVCR_AVEC2		(0x04)		
#define MCF5249_SIM_AVCR_AVEC1		(0x02)		
#define MCF5249_SIM_AVCR_BLK		(0x01)

#define MCF5249_SIM_DEVID_PART(a)	((a & 0xFFFFFF00) >> 8)
#define MCF5249_SIM_DEVID_MASK(a)	(a & 0x000000FF)


/**********************************************************************
*
* Phase-Locked Loop and Clock Dividers
*
***********************************************************************/

/* Offsets of the registers from the MBAR */
#define MCF5249_PLL_PLLCR		(*(vuint32 *)(void *)(&__MBAR2[0x180]))

/* Bit level definitions and macros */
#define MCF5249_PLL_PLLCR_LOCK		(0x80000000)	

/**********************************************************************
*
* Chip Select Registers
*
***********************************************************************/

/* Offsets of the registers from the MBAR */
#define	MCF5249_CS_CSAR0		(*(vuint16 *)(void *)(&__MBAR[0x080]))
#define	MCF5249_CS_CSMR0		(*(vuint32 *)(void *)(&__MBAR[0x084]))
#define	MCF5249_CS_CSCR0		(*(vuint16 *)(void *)(&__MBAR[0x08A]))
#define	MCF5249_CS_CSAR1		(*(vuint16 *)(void *)(&__MBAR[0x08C]))
#define	MCF5249_CS_CSMR1		(*(vuint32 *)(void *)(&__MBAR[0x090]))
#define	MCF5249_CS_CSCR1		(*(vuint16 *)(void *)(&__MBAR[0x096]))

/********************************************************************/
/********************************************************************/
/*** Added by Chris Baker 11/July/02 ***/

#define	MCF5249_CS_CSAR2		(*(vuint16 *)(void *)(&__MBAR[0x98]))	/* chip select address register 2 */
#define	MCF5249_CS_CSMR2		(*(vuint32 *)(void *)(&__MBAR[0x9C]))	/* chip select mask register 2 */
#define	MCF5249_CS_CSCR2		(*(vuint16 *)(void *)(&__MBAR[0xA2]))	/* chip select control register 2 */
#define	MCF5249_CS_CSAR3		(*(vuint16 *)(void *)(&__MBAR[0xA4]))	/* chip select address register 3 */
#define	MCF5249_CS_CSMR3		(*(vuint32 *)(void *)(&__MBAR[0xA8]))	/* chip select mask register 3 */
#define	MCF5249_CS_CSCR3		(*(vuint16 *)(void *)(&__MBAR[0xAE]))	/* chip select control register 3 */

/********************************************************************/
/********************************************************************/

/* Bit level definitions and macros */
#define MCF5249_CS_CSAR_BA(a)		(((a)&0xFFFF0000)>>16)

#define MCF5249_CS_CSMR_BAM_4G		(0xFFFF0000)
#define MCF5249_CS_CSMR_BAM_2G		(0x7FFF0000)
#define MCF5249_CS_CSMR_BAM_1G		(0x3FFF0000)
#define MCF5249_CS_CSMR_BAM_512M	(0x1FFF0000)
#define MCF5249_CS_CSMR_BAM_256M	(0x0FFF0000)
#define MCF5249_CS_CSMR_BAM_128M	(0x07FF0000)
#define MCF5249_CS_CSMR_BAM_64M		(0x03FF0000)
#define MCF5249_CS_CSMR_BAM_32M		(0x01FF0000)
#define MCF5249_CS_CSMR_BAM_16M		(0x00FF0000)
#define MCF5249_CS_CSMR_BAM_8M		(0x007F0000)
#define MCF5249_CS_CSMR_BAM_4M		(0x003F0000)
#define MCF5249_CS_CSMR_BAM_2M		(0x001F0000)
#define MCF5249_CS_CSMR_BAM_1M		(0x000F0000)
#define MCF5249_CS_CSMR_BAM_512K	(0x00070000)
#define MCF5249_CS_CSMR_BAM_256K	(0x00030000)
#define MCF5249_CS_CSMR_BAM_128K	(0x00010000)
#define MCF5249_CS_CSMR_BAM_64K		(0x00000000)

#define MCF5249_CS_CSMR_WP		(0x00000100)
#define MCF5249_CS_CSMR_AM		(0x00000040)
#define MCF5249_CS_CSMR_CI		(0x00000020)
#define MCF5249_CS_CSMR_SC		(0x00000010)
#define MCF5249_CS_CSMR_SD		(0x00000008)
#define MCF5249_CS_CSMR_UC		(0x00000004)
#define MCF5249_CS_CSMR_UD		(0x00000002)
#define MCF5249_CS_CSMR_V		(0x00000001)

#define MCF5249_CS_CSCR_WS(a)		((a & 0xF)<<10)
#define MCF5249_CS_CSCR_AA		(0x0100)
#define MCF5249_CS_CSCR_PS		(0x00C0)
#define MCF5249_CS_CSCR_BSTR		(0x0010)
#define MCF5249_CS_CSCR_BSTW		(0x0008)

/**********************************************************************
*
* Ports Registers Description
*
***********************************************************************/



/**********************************************************************
*
* QSPI Module Registers Description
*
***********************************************************************/

#define MCF5249_QSPI_QMR		(*(vuint32 *)(void *)(&__MBAR[0x400]))
#define MCF5249_QSPI_QDLYR		(*(vuint32 *)(void *)(&__MBAR[0x404]))
#define MCF5249_QSPI_QWR		(*(vuint32 *)(void *)(&__MBAR[0x408]))
#define MCF5249_QSPI_QIR		(*(vuint32 *)(void *)(&__MBAR[0x40C]))
#define MCF5249_QSPI_QAR		(*(vuint32 *)(void *)(&__MBAR[0x410]))
#define MCF5249_QSPI_QDR		(*(vuint32 *)(void *)(&__MBAR[0x414]))


/**********************************************************************
*
* DMA Module Registers Description
*
***********************************************************************/

#define	MCF5249_DMA_ROUTE		(*(vuint8  *)(void *)(&__MBAR2[0x188]))

#define MCF5249_DMA0_SAR		(*(vuint32 *)(void *)(&__MBAR[0x300]))	
#define MCF5249_DMA0_DAR		(*(vuint32 *)(void *)(&__MBAR[0x304]))	
#define MCF5249_DMA0_DCR		(*(vuint16 *)(void *)(&__MBAR[0x308]))	
#define MCF5249_DMA0_BCR		(*(vuint16 *)(void *)(&__MBAR[0x30C]))	
#define MCF5249_DMA0_DSR		(*(vuint8  *)(void *)(&__MBAR[0x310]))	
#define MCF5249_DMA0_DIVR		(*(vuint8  *)(void *)(&__MBAR[0x314]))	

#define MCF5249_DMA1_SAR		(*(vuint32 *)(void *)(&__MBAR[0x340]))	
#define MCF5249_DMA1_DAR		(*(vuint32 *)(void *)(&__MBAR[0x344]))	
#define MCF5249_DMA1_DCR		(*(vuint16 *)(void *)(&__MBAR[0x348]))	
#define MCF5249_DMA1_BCR		(*(vuint16 *)(void *)(&__MBAR[0x34C]))	
#define MCF5249_DMA1_DSR		(*(vuint8  *)(void *)(&__MBAR[0x350]))	
#define MCF5249_DMA1_DIVR		(*(vuint8  *)(void *)(&__MBAR[0x354]))	

#define MCF5249_DMA2_SAR		(*(vuint32 *)(void *)(&__MBAR[0x380]))	
#define MCF5249_DMA2_DAR		(*(vuint32 *)(void *)(&__MBAR[0x384]))	
#define MCF5249_DMA2_DCR		(*(vuint16 *)(void *)(&__MBAR[0x388]))	
#define MCF5249_DMA2_BCR		(*(vuint16 *)(void *)(&__MBAR[0x38C]))	
#define MCF5249_DMA2_DSR		(*(vuint8  *)(void *)(&__MBAR[0x390]))	
#define MCF5249_DMA2_DIVR		(*(vuint8  *)(void *)(&__MBAR[0x394]))	

#define MCF5249_DMA3_SAR		(*(vuint32 *)(void *)(&__MBAR[0x3C0]))	
#define MCF5249_DMA3_DAR		(*(vuint32 *)(void *)(&__MBAR[0x3C4]))	
#define MCF5249_DMA3_DCR		(*(vuint16 *)(void *)(&__MBAR[0x3C8]))	
#define MCF5249_DMA3_BCR		(*(vuint16 *)(void *)(&__MBAR[0x3CC]))	
#define MCF5249_DMA3_DSR		(*(vuint8  *)(void *)(&__MBAR[0x3D0]))	
#define MCF5249_DMA3_DIVR		(*(vuint8  *)(void *)(&__MBAR[0x3D4]))	

		
/**********************************************************************
*
* Mbus (IIC) Module Registers Description
*
***********************************************************************/

#define MCF5249_MBUS_MADR		(*(vuint8  *)(void *)(&__MBAR[0x280]))	
#define MCF5249_MBUS_MFDR		(*(vuint8  *)(void *)(&__MBAR[0x284]))	
#define MCF5249_MBUS_MBCR		(*(vuint8  *)(void *)(&__MBAR[0x288]))	
#define MCF5249_MBUS_MBSR		(*(vuint8  *)(void *)(&__MBAR[0x28C]))	
#define MCF5249_MBUS_MBDR		(*(vuint8  *)(void *)(&__MBAR[0x290]))	

#define MCF5249_MBUS2_MADR		(*(vuint8  *)(void *)(&__MBAR2[0x440]))	
#define MCF5249_MBUS2_MFDR		(*(vuint8  *)(void *)(&__MBAR2[0x444]))	
#define MCF5249_MBUS2_MBCR		(*(vuint8  *)(void *)(&__MBAR2[0x448]))	
#define MCF5249_MBUS2_MBSR		(*(vuint8  *)(void *)(&__MBAR2[0x44C]))	
#define MCF5249_MBUS2_MBDR		(*(vuint8  *)(void *)(&__MBAR2[0x450]))	

/**********************************************************************
*
* USART Module Registers Description
*
***********************************************************************/

#define MCF5249_UART0_UMR		(*(vuint8  *)(void *)(&__MBAR[0x1C0]))
#define MCF5249_UART0_USR		(*(vuint8  *)(void *)(&__MBAR[0x1C4]))
#define MCF5249_UART0_UCSR		(*(vuint8  *)(void *)(&__MBAR[0x1C4]))
#define MCF5249_UART0_UCR		(*(vuint8  *)(void *)(&__MBAR[0x1C8]))
#define MCF5249_UART0_URB		(*(vuint8  *)(void *)(&__MBAR[0x1CC]))
#define MCF5249_UART0_UTB		(*(vuint8  *)(void *)(&__MBAR[0x1CC]))
#define MCF5249_UART0_UIPCR		(*(vuint8  *)(void *)(&__MBAR[0x1D0]))
#define MCF5249_UART0_UACR		(*(vuint8  *)(void *)(&__MBAR[0x1D0]))
#define MCF5249_UART0_UISR		(*(vuint8  *)(void *)(&__MBAR[0x1D4]))
#define MCF5249_UART0_UIMR		(*(vuint8  *)(void *)(&__MBAR[0x1D4]))
#define MCF5249_UART0_UBG1		(*(vuint8  *)(void *)(&__MBAR[0x1D8]))
#define MCF5249_UART0_UBG2		(*(vuint8  *)(void *)(&__MBAR[0x1DC]))
#define MCF5249_UART0_UIVR		(*(vuint8  *)(void *)(&__MBAR[0x1F0]))
#define MCF5249_UART0_UIP		(*(vuint8  *)(void *)(&__MBAR[0x1F4]))
#define MCF5249_UART0_UOP1		(*(vuint8  *)(void *)(&__MBAR[0x1F8]))
#define MCF5249_UART0_UOP0		(*(vuint8  *)(void *)(&__MBAR[0x1FC]))

#define MCF5249_UART1_UMR		(*(vuint8  *)(void *)(&__MBAR[0x200]))
#define MCF5249_UART1_USR		(*(vuint8  *)(void *)(&__MBAR[0x204]))
#define MCF5249_UART1_UCSR		(*(vuint8  *)(void *)(&__MBAR[0x204]))
#define MCF5249_UART1_UCR		(*(vuint8  *)(void *)(&__MBAR[0x208]))
#define MCF5249_UART1_URB		(*(vuint8  *)(void *)(&__MBAR[0x20C]))
#define MCF5249_UART1_UTB		(*(vuint8  *)(void *)(&__MBAR[0x20C]))
#define MCF5249_UART1_UIPCR		(*(vuint8  *)(void *)(&__MBAR[0x210]))
#define MCF5249_UART1_UACR		(*(vuint8  *)(void *)(&__MBAR[0x210]))
#define MCF5249_UART1_UISR		(*(vuint8  *)(void *)(&__MBAR[0x214]))
#define MCF5249_UART1_UIMR		(*(vuint8  *)(void *)(&__MBAR[0x214]))
#define MCF5249_UART1_UBG1		(*(vuint8  *)(void *)(&__MBAR[0x218]))
#define MCF5249_UART1_UBG2		(*(vuint8  *)(void *)(&__MBAR[0x21C]))
#define MCF5249_UART1_UIVR		(*(vuint8  *)(void *)(&__MBAR[0x230]))
#define MCF5249_UART1_UIP		(*(vuint8  *)(void *)(&__MBAR[0x234]))
#define MCF5249_UART1_UOP1		(*(vuint8  *)(void *)(&__MBAR[0x238]))
#define MCF5249_UART1_UOP0		(*(vuint8  *)(void *)(&__MBAR[0x23C]))


/* Bit level definitions and macros */
#define MCF5249_UART_UMR1_RXRTS			(0x80)
#define MCF5249_UART_UMR1_RXIRQ			(0x40)
#define MCF5249_UART_UMR1_ERR			(0x20)
#define MCF5249_UART_UMR1_PM_MULTI_ADDR		(0x1C)
#define MCF5249_UART_UMR1_PM_MULTI_DATA		(0x18)
#define MCF5249_UART_UMR1_PM_NONE		(0x10)
#define MCF5249_UART_UMR1_PM_FORCE_HI		(0x0C)
#define MCF5249_UART_UMR1_PM_FORCE_LO		(0x08)
#define MCF5249_UART_UMR1_PM_ODD		(0x04)
#define MCF5249_UART_UMR1_PM_EVEN		(0x00)
#define MCF5249_UART_UMR1_BC_5			(0x00)
#define MCF5249_UART_UMR1_BC_6			(0x01)
#define MCF5249_UART_UMR1_BC_7			(0x02)
#define MCF5249_UART_UMR1_BC_8			(0x03)