📄 mcf5249.h
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/*
* File: mcf5249.h
* Purpose: MCF5249 definitions
*
* Notes: Based on Rev 0.3 of the MCF5249 User's Manual
*
*/
#ifndef _CPU_MCF5249_H
#define _CPU_MCF5249_H
/********************************************************************/
/*
* The basic data types
*/
typedef unsigned char uint8; /* 8 bits */
typedef unsigned short int uint16; /* 16 bits */
typedef unsigned long int uint32; /* 32 bits */
typedef signed char int8; /* 8 bits */
typedef signed short int int16; /* 16 bits */
typedef signed long int int32; /* 32 bits */
typedef volatile uint8 vuint8; /* 8 bits */
typedef volatile uint16 vuint16; /* 16 bits */
typedef volatile uint32 vuint32; /* 32 bits */
/********************************************************************/
/*
* Memory map definitions from linker command files
*/
extern uint8 __MBAR[];
extern uint8 __MBAR2[];
extern uint8 __SRAM0[];
extern uint8 __SRAM1[];
/********************************************************************/
/*
* Functions provided by mcf5249_lo.s
*/
int asm_set_ipl (uint32);
void mcf5249_wr_vbr (uint32);
void mcf5249_wr_cacr (uint32);
void mcf5249_wr_acr0 (uint32);
void mcf5249_wr_acr1 (uint32);
void mcf5249_wr_sr (uint32);
/********************************************************************/
/*
* Misc. Defines
*/
#ifdef FALSE
#undef FALSE
#endif
#define FALSE (0)
#ifdef TRUE
#undef TRUE
#endif
#define TRUE (1)
#ifdef NULL
#undef NULL
#endif
#define NULL (0)
/********************************************************************/
/*
* Common M68K & ColdFire definitions
*/
#define ADDRESS uint32
#define INSTRUCTION uint16
#define ILLEGAL 0x4AFC
#define CPU_WORD_SIZE 16
/********************************************************************/
/*
* Routines and macros for accessing Input/Output devices
*/
#define cpu_iord_8(ADDR) *((vuint8 *)(ADDR))
#define cpu_iord_16(ADDR) *((vuint16 *)(ADDR))
#define cpu_iord_32(ADDR) *((vuint32 *)(ADDR))
#define cpu_iowr_8(ADDR,DATA) *((vuint8 *)(ADDR)) = (DATA)
#define cpu_iowr_16(ADDR,DATA) *((vuint16 *)(ADDR)) = (DATA)
#define cpu_iowr_32(ADDR,DATA) *((vuint32 *)(ADDR)) = (DATA)
/********************************************************************/
#define MCF5200_SR_T (0x8000)
#define MCF5200_SR_S (0x2000)
#define MCF5200_SR_M (0x1000)
#define MCF5200_SR_IPL (0x0700)
#define MCF5200_SR_IPL_0 (0x0000)
#define MCF5200_SR_IPL_1 (0x0100)
#define MCF5200_SR_IPL_2 (0x0200)
#define MCF5200_SR_IPL_3 (0x0300)
#define MCF5200_SR_IPL_4 (0x0400)
#define MCF5200_SR_IPL_5 (0x0500)
#define MCF5200_SR_IPL_6 (0x0600)
#define MCF5200_SR_IPL_7 (0x0700)
#define MCF5200_SR_X (0x0010)
#define MCF5200_SR_N (0x0008)
#define MCF5200_SR_Z (0x0004)
#define MCF5200_SR_V (0x0002)
#define MCF5200_SR_C (0x0001)
/********************************************************************/
/*
* The ColdFire family of processors has a simplified exception stack
* frame that looks like the following:
*
* 8 +----------------+----------------+
* | Program Counter |
* 4 +----------------+----------------+
* |FS/Fmt/Vector/FS| SR |
* SP --> 0 +----------------+----------------+
*
* The stack self-aligns to a 4-byte boundary at an exception, with
* the FS/Fmt/Vector/FS field indicating the size of the adjustment
* (SP += 0,1,2,3 bytes).
*/
#define MCF5200_RD_SF_FORMAT(PTR) \
((*((uint16 *)(PTR)) >> 12) & 0x00FF)
#define MCF5200_RD_SF_VECTOR(PTR) \
((*((uint16 *)(PTR)) >> 2) & 0x00FF)
#define MCF5200_RD_SF_FS(PTR) \
( ((*((uint16 *)(PTR)) & 0x0C00) >> 8) | (*((uint16 *)(PTR)) & 0x0003) )
#define MCF5200_SF_SR(PTR) *((uint16 *)(PTR)+1)
#define MCF5200_SF_PC(PTR) *((uint32 *)(PTR)+1)
/********************************************************************
*
* Local Memories
*
*********************************************************************/
/* Bit level definitions and macros */
#define MCF5249_CACR_CENB (0x80000000)
#define MCF5249_CACR_CPDI (0x10000000)
#define MCF5249_CACR_CFRZ (0x08000000)
#define MCF5249_CACR_CINV (0x01000000)
#define MCF5249_CACR_CEIB (0x00000400)
#define MCF5249_CACR_DCM (0x00000200)
#define MCF5249_CACR_DBWE (0x00000100)
#define MCF5249_CACR_DWP (0x00000040)
#define MCF5249_CACR_CLNF_00 (0x00000000)
#define MCF5249_CACR_CLNF_01 (0x00000002)
#define MCF5249_CACR_CLNF_10 (0x00000004)
#define MCF5249_CACR_CLNF_11 (0x00000006)
#define MCF5249_ACR_AB(a) ((a)&0xFF000000)
#define MCF5249_ACR_AM(a) (((a)&0xFF000000) >> 8)
#define MCF5249_ACR_EN (0x00008000)
#define MCF5249_ACR_SM_USER (0x00000000)
#define MCF5249_ACR_SM_SUPER (0x00002000)
#define MCF5249_ACR_SM_IGNORE (0x00006000)
#define MCF5249_ACR_ENIB (0x00000080)
#define MCF5249_ACR_CM (0x00000040)
#define MCF5249_ACR_BWE (0x00000020)
#define MCF5249_ACR_WP (0x00000004)
#define MCF5249_RAMBAR_BA(a) ((a)&0xFFFFC000)
#define MCF5249_RAMBAR_PRI_00 (0x00000000)
#define MCF5249_RAMBAR_PRI_01 (0x00004000)
#define MCF5249_RAMBAR_PRI_10 (0x00008000)
#define MCF5249_RAMBAR_PRI_11 (0x0000C000)
#define MCF5249_RAMBAR_WP (0x00000100)
#define MCF5249_RAMBAR_CI (0x00000020)
#define MCF5249_RAMBAR_SC (0x00000010)
#define MCF5249_RAMBAR_SD (0x00000008)
#define MCF5249_RAMBAR_UC (0x00000004)
#define MCF5249_RAMBAR_UD (0x00000002)
#define MCF5249_RAMBAR_V (0x00000001)
/*********************************************************************
*
* System Configuration Registers (SIM)
*
*********************************************************************/
#define MCF5249_SIM_RSR (*(vuint8 *)(void *)(&__MBAR[0x00]))
#define MCF5249_SIM_SYPCR (*(vuint8 *)(void *)(&__MBAR[0x01]))
#define MCF5249_SIM_SWIVR (*(vuint8 *)(void *)(&__MBAR[0x02]))
#define MCF5249_SIM_SWSR (*(vuint8 *)(void *)(&__MBAR[0x03]))
#define MCF5249_SIM_IRQPAR (*(vuint8 *)(void *)(&__MBAR[0x06]))
#define MCF5249_SIM_MPARK (*(vuint8 *)(void *)(&__MBAR[0x0C]))
#define MCF5249_SIM_IPR (*(vuint32 *)(void *)(&__MBAR[0x40]))
#define MCF5249_SIM_IMR (*(vuint32 *)(void *)(&__MBAR[0x44]))
#define MCF5249_SIM_AVCR (*(vuint8 *)(void *)(&__MBAR[0x51]))
#define MCF5249_SIM_ICR0 (*(vuint8 *)(void *)(&__MBAR[0x4C]))
#define MCF5249_SIM_ICR1 (*(vuint8 *)(void *)(&__MBAR[0x4D]))
#define MCF5249_SIM_ICR2 (*(vuint8 *)(void *)(&__MBAR[0x4E]))
#define MCF5249_SIM_ICR3 (*(vuint8 *)(void *)(&__MBAR[0x4F]))
#define MCF5249_SIM_ICR4 (*(vuint8 *)(void *)(&__MBAR[0x50]))
#define MCF5249_SIM_ICR5 (*(vuint8 *)(void *)(&__MBAR[0x51]))
#define MCF5249_SIM_ICR6 (*(vuint8 *)(void *)(&__MBAR[0x52]))
#define MCF5249_SIM_ICR7 (*(vuint8 *)(void *)(&__MBAR[0x53]))
#define MCF5249_SIM_ICR8 (*(vuint8 *)(void *)(&__MBAR[0x54]))
#define MCF5249_SIM_ICR9 (*(vuint8 *)(void *)(&__MBAR[0x55]))
#define MCF5249_SIM_GPIO_READ (*(vuint32 *)(void *)(&__MBAR2[0x00]))
#define MCF5249_SIM_GPIO_OUT (*(vuint32 *)(void *)(&__MBAR2[0x04]))
#define MCF5249_SIM_GPIO_ENABLE (*(vuint32 *)(void *)(&__MBAR2[0x08]))
#define MCF5249_SIM_GPIO_FUNC (*(vuint32 *)(void *)(&__MBAR2[0x0C]))
#define MCF5249_SIM_DEVID (*(vuint32 *)(void *)(&__MBAR2[0xAC]))
#define MCF5249_SIM_GPIO1_READ (*(vuint32 *)(void *)(&__MBAR2[0xB0]))
#define MCF5249_SIM_GPIO1_OUT (*(vuint32 *)(void *)(&__MBAR2[0xB4]))
#define MCF5249_SIM_GPIO1_ENABLE (*(vuint32 *)(void *)(&__MBAR2[0xB8]))
#define MCF5249_SIM_GPIO1_FUNC (*(vuint32 *)(void *)(&__MBAR2[0xBC]))
#define MCF5249_SIM_GPIO_INT_STAT (*(vuint32 *)(void *)(&__MBAR2[0xC0]))
#define MCF5249_SIM_GPIO_INT_CLEAR (*(vuint32 *)(void *)(&__MBAR2[0xC0]))
#define MCF5249_SIM_GPIO_INT_EN (*(vuint32 *)(void *)(&__MBAR2[0xC4]))
#define MCF5249_SIM_INTERRUPT_STAT3 (*(vuint32 *)(void *)(&__MBAR2[0xE0]))
#define MCF5249_SIM_INTERRUPT_CLR3 (*(vuint32 *)(void *)(&__MBAR2[0xE0]))
#define MCF5249_SIM_INTERRUPT_EN3 (*(vuint32 *)(void *)(&__MBAR2[0xE4]))
#define MCF5249_SIM_INTLEV1 (*(vuint32 *)(void *)(&__MBAR2[0x140]))
#define MCF5249_SIM_INTLEV2 (*(vuint32 *)(void *)(&__MBAR2[0x144]))
#define MCF5249_SIM_INTLEV3 (*(vuint32 *)(void *)(&__MBAR2[0x148]))
#define MCF5249_SIM_INTLEV4 (*(vuint32 *)(void *)(&__MBAR2[0x14C]))
#define MCF5249_SIM_INTLEV5 (*(vuint32 *)(void *)(&__MBAR2[0x150]))
#define MCF5249_SIM_INTLEV6 (*(vuint32 *)(void *)(&__MBAR2[0x154]))
#define MCF5249_SIM_INTLEV7 (*(vuint32 *)(void *)(&__MBAR2[0x158]))
#define MCF5249_SIM_INTLEV8 (*(vuint32 *)(void *)(&__MBAR2[0x15C]))
#define MCF5249_SIM_SPURVEC (*(vuint32 *)(void *)(&__MBAR2[0x164]))
#define MCF5249_SIM_INTBASE (*(vuint8 *)(void *)(&__MBAR2[0x16B]))
/* Bit level definitions and macros */
#define MCF5249_SIM_RSR_HRST (0x80)
#define MCF5249_SIM_RSR_SWTR (0x20)
#define MCF5249_SIM_SYPCR_SWE (0x80)
#define MCF5249_SIM_SYPCR_SWRI (0x40)
#define MCF5249_SIM_SYPCR_SWT_2_9 (0x00)
#define MCF5249_SIM_SYPCR_SWT_2_11 (0x08)
#define MCF5249_SIM_SYPCR_SWT_2_13 (0x10)
#define MCF5249_SIM_SYPCR_SWT_2_15 (0x18)
#define MCF5249_SIM_SYPCR_SWT_2_18 (0x20)
#define MCF5249_SIM_SYPCR_SWT_2_20 (0x28)
#define MCF5249_SIM_SYPCR_SWT_2_22 (0x30)
#define MCF5249_SIM_SYPCR_SWT_2_24 (0x38)
#define MCF5249_SIM_SYPCR_SWTA (0x04)
#define MCF5249_SIM_SYPCR_SWTAVAL (0x02)
#define MCF5249_SIM_SWSR_55 (0x55)
#define MCF5249_SIM_SWSR_AA (0xaa)
#define MCF5249_MBAR_BA(a) ((a)&0xFFFFF000)
#define MCF5249_MBAR_WP (0x00000100)
#define MCF5249_MBAR_AM (0x00000040)
#define MCF5249_MBAR_CI (0x00000020)
#define MCF5249_MBAR_SC (0x00000010)
#define MCF5249_MBAR_SD (0x00000008)
#define MCF5249_MBAR_UC (0x00000004)
#define MCF5249_MBAR_UD (0x00000002)
#define MCF5249_MBAR_V (0x00000001)
#define MCF5249_MBAR2_BA(a) ((a)&0xC0000000)
#define MCF5249_MBAR2_LS7 (0x00000080)
#define MCF5249_MBAR2_LS6 (0x00000040)
#define MCF5249_MBAR2_LS5 (0x00000020)
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