pwr_amp_1.mdl

PLLmatlab for simulink

	  SourceType		  "Parallel RLC Branch"
	  PhysicalDomain	  "powersysdomain"
	  SubClassName		  "unknown"
	  LeftPortType		  "p1"
	  RightPortType		  "p1"
	  LConnTagsString	  "a"
	  RConnTagsString	  "__new0"
	  Resistance		  "inf"
	  Inductance		  "L4"
	  Capacitance		  "0"
	  Measurements		  "None"
	}
	Block {
	  BlockType		  PMIOPort
	  Name			  "in"
	  Position		  [55, 28, 85, 42]
	  Port			  "1"
	  Side			  "Left"
	}
	Block {
	  BlockType		  PMIOPort
	  Name			  "out"
	  Position		  [480, 28, 510, 42]
	  Orientation		  "left"
	  Port			  "2"
	  Side			  "Right"
	}
	Line {
	  LineType		  "Connection"
	  SrcBlock		  "C3"
	  SrcPort		  LConn1
	  Points		  [0, 5; -55, 0]
	  Branch {
	    ConnectType		    "DEST_SRC"
	    Points		    [-75, 0]
	    DstBlock		    "C1"
	    DstPort		    LConn1
	  }
	  Branch {
	    ConnectType		    "DEST_SRC"
	    DstBlock		    "G5"
	    DstPort		    LConn1
	  }
	}
	Line {
	  LineType		  "Connection"
	  SrcBlock		  "C3"
	  SrcPort		  RConn1
	  Points		  [0, 0; 0, -30]
	  Branch {
	    ConnectType		    "DEST_SRC"
	    DstBlock		    "L2"
	    DstPort		    RConn1
	  }
	  Branch {
	    ConnectType		    "DEST_SRC"
	    DstBlock		    "L4"
	    DstPort		    LConn1
	  }
	}
	Line {
	  LineType		  "Connection"
	  SrcBlock		  "out"
	  SrcPort		  RConn1
	  DstBlock		  "L4"
	  DstPort		  RConn1
	}
	Line {
	  LineType		  "Connection"
	  SrcBlock		  "in"
	  SrcPort		  RConn1
	  Points		  [0, 0; 105, 0]
	  Branch {
	    ConnectType		    "DEST_SRC"
	    DstBlock		    "C1"
	    DstPort		    RConn1
	  }
	  Branch {
	    ConnectType		    "DEST_SRC"
	    DstBlock		    "L2"
	    DstPort		    LConn1
	  }
	}
      }
    }
    Block {
      BlockType		      Reference
      Name		      "Load"
      Ports		      [0, 0, 0, 0, 0, 1, 1]
      Position		      [774, 105, 796, 150]
      Orientation	      "down"
      NamePlacement	      "alternate"
      AttributesFormatString  "\\n"
      SourceBlock	      "powerlib/Elements/Parallel RLC Branch"
      SourceType	      "Parallel RLC Branch"
      PhysicalDomain	      "powersysdomain"
      SubClassName	      "unknown"
      LeftPortType	      "p1"
      RightPortType	      "p1"
      LConnTagsString	      "a"
      RConnTagsString	      "__new0"
      Resistance	      "8"
      Inductance	      "inf"
      Capacitance	      "0"
      Measurements	      "None"
    }
    Block {
      BlockType		      TransferFcn
      Name		      "Loop Compensator"
      Position		      [290, 237, 390, 283]
      Orientation	      "left"
      Numerator		      "[ 0.000001 1]*2e-1"
      Denominator	      "[.00001 0]"
      Port {
	PortNumber		1
	Name			"pulse duration drive signal"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Constant
      Name		      "Offset"
      Position		      [395, 370, 425, 400]
      Value		      "15"
    }
    Block {
      BlockType		      Saturate
      Name		      "Sat"
      Position		      [255, 140, 285, 170]
      UpperLimit	      "0.95"
      LowerLimit	      ".01"
    }
    Block {
      BlockType		      Scope
      Name		      "Scope1"
      Ports		      [3]
      Position		      [905, 253, 935, 287]
      Location		      [406, 278, 1019, 729]
      Open		      on
      NumInputPorts	      "3"
      ZoomMode		      "xonly"
      List {
	ListType		AxesTitles
	axes1			"%<SignalLabel>"
	axes2			"%<SignalLabel>"
	axes3			"%<SignalLabel>"
      }
      TimeRange		      "0.01"
      YMin		      "0~-15~0.1"
      YMax		      "30~20~0.9"
      SaveName		      "ScopeData2"
      DataFormat	      "StructureWithTime"
    }
    Block {
      BlockType		      SubSystem
      Name		      "Signal Spectrum"
      Description	      "Spectrum Analyzer"
      Ports		      [1]
      Position		      [565, 276, 775, 314]
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      MaskPromptString	      "Bandwidth"
      MaskStyleString	      "edit"
      MaskTunableValueString  "on"
      MaskEnableString	      "on"
      MaskVisibilityString    "on"
      MaskToolTipString	      "on"
      MaskVariables	      "BW=@1;"
      MaskDisplay	      "fprintf('Baseband Spectrum Analyzer \\n  BW=%7."
"2f MHz', BW/1e6)"
      MaskIconFrame	      on
      MaskIconOpaque	      on
      MaskIconRotate	      "none"
      MaskIconUnits	      "autoscale"
      MaskValueString	      "20e3"
      System {
	Name			"Signal Spectrum"
	Location		[106, 433, 642, 669]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "Input Signal"
	  Position		  [50, 52, 90, 68]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "Spectrum\nScope"
	  Ports			  [1]
	  Position		  [280, 35, 315, 85]
	  SourceBlock		  "dspsnks4/Spectrum\nScope"
	  SourceType		  "Spectrum Scope"
	  ShowPortLabels	  off
	  ScopeProperties	  on
	  Domain		  "Frequency"
	  HorizSpan		  "1"
	  UseBuffer		  on
	  BufferSize		  "512"
	  Overlap		  "0"
	  inpFftLenInherit	  off
	  FFTlength		  "128"
	  numAvg		  "1"
	  DisplayProperties	  off
	  AxisGrid		  on
	  Memory		  off
	  FrameNumber		  on
	  AxisLegend		  off
	  AxisZoom		  off
	  OpenScopeAtSimStart	  on
	  OpenScopeImmediately	  off
	  FigPos		  "[7 35 398 272]"
	  AxisProperties	  off
	  XUnits		  "Hertz"
	  XRange		  "[0...Fs/2]"
	  InheritXIncr		  on
	  XIncr			  "1.0"
	  XLabel		  "Samples"
	  YUnits		  "dB"
	  YMin			  "-60"
	  YMax			  "60"
	  YLabel		  "Magnitude, dB"
	  LineProperties	  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "anti alias"
	  Ports			  [1, 1]
	  Position		  [115, 32, 180, 88]
	  SourceBlock		  "dsparch4/Analog\nFilter Design"
	  SourceType		  "Analog Filter Design"
	  method		  "Elliptic"
	  filttype		  "Lowpass"
	  N			  "8"
	  Wlo			  "BW*2*pi"
	  Whi			  "80"
	  Rp			  "0.11"
	  Rs			  "100"
	}
	Block {
	  BlockType		  ZeroOrderHold
	  Name			  "sampler"
	  Position		  [210, 41, 245, 79]
	  SampleTime		  "1/(2.56*BW)"
	}
	Line {
	  SrcBlock		  "sampler"
	  SrcPort		  1
	  DstBlock		  "Spectrum\nScope"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "anti alias"
	  SrcPort		  1
	  DstBlock		  "sampler"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Input Signal"
	  SrcPort		  1
	  DstBlock		  "anti alias"
	  DstPort		  1
	}
      }
    }
    Block {
      BlockType		      Sin
      Name		      "Sine Waves"
      Ports		      [0, 1]
      Position		      [585, 370, 615, 400]
      Orientation	      "left"
      SineType		      "Time based"
      Amplitude		      "5"
      Frequency		      "2*pi*[2000,2500]"
      SampleTime	      "0"
    }
    Block {
      BlockType		      Reference
      Name		      "Slider\nGain"
      Ports		      [1, 1]
      Position		      [115, 130, 160, 160]
      SourceBlock	      "simulink/Math\nOperations/Slider\nGain"
      SourceType	      "Slider Gain"
      ShowPortLabels	      on
      low		      "0"
      gain		      "0.5"
      high		      "1"
    }
    Block {
      BlockType		      Sum
      Name		      "Sum"
      Ports		      [2, 1]
      Position		      [465, 250, 485, 270]
      Orientation	      "left"
      ShowName		      off
      IconShape		      "round"
      Inputs		      "|-+"
      Port {
	PortNumber		1
	Name			"Error"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
    }
    Block {
      BlockType		      Sum
      Name		      "Sum1"
      Ports		      [1, 1]
      Position		      [525, 375, 545, 395]
      Orientation	      "left"
      ShowName		      off
      IconShape		      "round"
      Inputs		      "+"
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      Sum
      Name		      "Sum2"
      Ports		      [2, 1]
      Position		      [465, 375, 485, 395]
      Orientation	      "up"
      NamePlacement	      "alternate"
      ShowName		      off
      IconShape		      "round"
      InputSameDT	      off
      OutDataTypeMode	      "Inherit via internal rule"
      SaturateOnIntegerOverflow	off
    }
    Block {
      BlockType		      SubSystem
      Name		      "Variable Duration One Shot"
      Ports		      [2, 2]
      Position		      [385, 108, 470, 172]
      FontSize		      10
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      Port {
	PortNumber		2
	Name			"gate_drive"
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      System {
	Name			"Variable Duration One Shot"
	Location		[199, 179, 781, 494]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "Trigger"
	  Position		  [15, 138, 45, 152]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Inport
	  Name			  "Ton"
	  Position		  [380, 153, 410, 167]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  Reference
	  Name			  "D Flip-Flop"
	  Ports			  [3, 2]
	  Position		  [155, 107, 200, 183]
	  SourceBlock		  "simulink_extras/Flip Flops/D Flip-Flop"
	  SourceType		  "DFlipFlop"
	  ShowPortLabels	  on
	}
	Block {
	  BlockType		  Integrator
	  Name			  "Integrator"
	  Ports			  [2, 1]
	  Position		  [270, 103, 360, 187]
	  ExternalReset		  "level"
	}
	Block {
	  BlockType		  Logic
	  Name			  "Logical\nOperator"
	  Ports			  [1, 1]
	  Position		  [95, 154, 125, 186]
	  Operator		  "NOT"
	}
	Block {
	  BlockType		  RelationalOperator
	  Name			  "Relational\nOperator"
	  Position		  [440, 137, 470, 168]
	  NamePlacement		  "alternate"
	}
	Block {
	  BlockType		  TransportDelay
	  Name			  "Transport\nDelay"
	  Position		  [105, 25, 135, 55]
	  Orientation		  "left"
	  DelayTime		  "10e-9"
	}
	Block {
	  BlockType		  Constant
	  Name			  "logic 1"
	  Position		  [100, 111, 120, 129]
	}
	Block {
	  BlockType		  Outport
	  Name			  "Pulse Out"
	  Position		  [525, 68, 555, 82]
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Block {
	  BlockType		  Outport
	  Name			  "Pulse Out1"
	  Position		  [520, 203, 550, 217]
	  Port			  "2"
	  IconDisplay		  "Port number"
	  BusOutputAsStruct	  off
	}
	Line {
	  SrcBlock		  "D Flip-Flop"
	  SrcPort		  2
	  Points		  [30, 0]
	  Branch {
	    DstBlock		    "Integrator"
	    DstPort		    2
	  }
	  Branch {
	    Points		    [0, 45]
	    DstBlock		    "Pulse Out1"
	    DstPort		    1
	  }
	}
	Line {
	  SrcBlock		  "logic 1"
	  SrcPort		  1
	  DstBlock		  "D Flip-Flop"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Relational\nOperator"
	  SrcPort		  1
	  Points		  [15, 0; 0, -115]
	  DstBlock		  "Transport\nDelay"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "Logical\nOperator"
	  SrcPort		  1
	  DstBlock		  "D Flip-Flop"
	  DstPort		  3
	}
	Line {
	  SrcBlock		  "Integrator"
	  SrcPort		  1
	  DstBlock		  "Relational\nOperator"
	  DstPort		  1
	}
	Line {
	  SrcBlock		  "D Flip-Flop"
	  SrcPort		  1
	  Points		  [0, 0; 30, 0]
	  Branch {
	    DstBlock		    "Integrator"
	    DstPort		    1
	  }
	  Branch {
	    Points		    [0, -50]
	    DstBlock		    "Pulse Out"
	    DstPort		    1