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📄 sigma2nd_d.mdl

📁 PLLmatlab for simulink
💻 MDL
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      AxisLegend	      off
      AxisZoom		      off
      OpenScopeAtSimStart     on
      OpenScopeImmediately    off
      FigPos		      "[444 39 414 275]"
      AxisProperties	      off
      XUnits		      "Hertz"
      XRange		      "[0...Fs/2]"
      InheritXIncr	      on
      XIncr		      "64/Fs"
      XLabel		      "Samples"
      YUnits		      "dB"
      YMin		      "-80"
      YMax		      "10"
      YLabel		      "Magnitude, dB"
      LineProperties	      off
    }
    Block {
      BlockType		      SubSystem
      Name		      "Switched Capacitor  2nd Order Modulator"
      Ports		      [1, 3]
      Position		      [180, 100, 330, 190]
      TreatAsAtomicUnit	      off
      MinAlgLoopOccurrences   off
      RTWSystemCode	      "Auto"
      Port {
	PortNumber		1
	Name			"Clocks"
	PropagatedSignals	"Clk_0, Clk_1, "
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      Port {
	PortNumber		2
	Name			"Test Points"
	PropagatedSignals	", , , , "
	RTWStorageClass		"Auto"
	DataLoggingNameMode	"SignalName"
	ShowSigGenPortName	on
      }
      System {
	Name			"Switched Capacitor  2nd Order Modulator"
	Location		[40, 294, 1025, 855]
	Open			off
	ModelBrowserVisibility	off
	ModelBrowserWidth	200
	ScreenColor		"white"
	PaperOrientation	"landscape"
	PaperPositionMode	"auto"
	PaperType		"usletter"
	PaperUnits		"inches"
	ZoomFactor		"100"
	Block {
	  BlockType		  Inport
	  Name			  "Analog In"
	  Position		  [15, 328, 45, 342]
	  Port			  "1"
	  IconDisplay		  "Port number"
	  LatchInput		  off
	}
	Block {
	  BlockType		  DiscretePulseGenerator
	  Name			  "Clk Phase 1"
	  Ports			  [0, 1]
	  Position		  [35, 88, 80, 122]
	  PulseType		  "Time based"
	  Period		  "1/Fs"
	  PulseWidth		  "49.9"
	  PhaseDelay		  "0.001/Fs"
	  Port {
	    PortNumber		    1
	    Name		    "Clk_1"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	    ShowSigGenPortName	    on
	  }
	}
	Block {
	  BlockType		  DiscretePulseGenerator
	  Name			  "Clk Phase 2"
	  Ports			  [0, 1]
	  Position		  [35, 138, 80, 172]
	  PulseType		  "Time based"
	  Period		  "1/Fs"
	  PulseWidth		  "50.1"
	  Port {
	    PortNumber		    1
	    Name		    "Clk_2"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	    ShowSigGenPortName	    on
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Differential Driver"
	  Ports			  [1, 0, 0, 0, 0, 0, 2]
	  Position		  [65, 305, 115, 360]
	  TreatAsAtomicUnit	  off
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  System {
	    Name		    "Differential Driver"
	    Location		    [437, 269, 803, 634]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In"
	      Position		      [15, 43, 45, 57]
	      Port		      "1"
	      IconDisplay	      "Port number"
	      LatchInput	      off
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "CVS1"
	      Description	      "source block"
	      Ports		      [1, 0, 0, 0, 0, 1, 1]
	      Position		      [175, 35, 215, 90]
	      AttributesFormatString  "\\n"
	      SourceBlock	      "powerlib/Electrical\nSources/Controlled"
" Voltage Source"
	      SourceType	      "Controlled Voltage Source"
	      ShowPortLabels	      on
	      Initialize	      off
	      SourceType	      "AC"
	      Amplitude		      "0"
	      Phase		      "0"
	      Frequency		      "0"
	      Measurements	      "None"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "CVS2"
	      Description	      "source block"
	      Ports		      [1, 0, 0, 0, 0, 1, 1]
	      Position		      [170, 152, 210, 208]
	      AttributesFormatString  "\\n"
	      SourceBlock	      "powerlib/Electrical\nSources/Controlled"
" Voltage Source"
	      SourceType	      "Controlled Voltage Source"
	      ShowPortLabels	      on
	      Initialize	      off
	      SourceType	      "AC"
	      Amplitude		      "0"
	      Phase		      "0"
	      Frequency		      "0"
	      Measurements	      "None"
	    }
	    Block {
	      BlockType		      Reference
	      Name		      "G1"
	      Ports		      [0, 0, 0, 0, 0, 1]
	      Position		      [124, 250, 146, 275]
	      Orientation	      "down"
	      AttributesFormatString  "\\n"
	      SourceBlock	      "powerlib/Elements/Ground"
	      SourceType	      "Ground"
	      PhysicalDomain	      "powersysdomain"
	      SubClassName	      "unknown"
	      LeftPortType	      "p1"
	      RightPortType	      "p1"
	      LConnTagsString	      "a"
	    }
	    Block {
	      BlockType		      Gain
	      Name		      "Gain1"
	      Position		      [65, 31, 100, 69]
	      Gain		      "0.5"
	    }
	    Block {
	      BlockType		      PMIOPort
	      Name		      "+"
	      Position		      [295, 58, 325, 72]
	      Orientation	      "left"
	      Port		      "1"
	      Side		      "Right"
	    }
	    Block {
	      BlockType		      PMIOPort
	      Name		      "-"
	      Position		      [300, 173, 330, 187]
	      Orientation	      "left"
	      Port		      "2"
	      Side		      "Right"
	    }
	    Line {
	      LineType		      "Connection"
	      Points		      [135, 130; 0, -55; 25, 0]
	      DstBlock		      "CVS1"
	      DstPort		      LConn1
	      Branch {
		ConnectType		"SRC_DEST"
		SrcBlock		"CVS2"
		SrcPort			RConn1
		Points			[0, -50; -90, 0]
	      }
	      Branch {
		ConnectType		"SRC_SRC"
		DstBlock		"G1"
		DstPort			LConn1
	      }
	    }
	    Line {
	      SrcBlock		      "In"
	      SrcPort		      1
	      DstBlock		      "Gain1"
	      DstPort		      1
	    }
	    Line {
	      LineType		      "Connection"
	      SrcBlock		      "+"
	      SrcPort		      RConn1
	      DstBlock		      "CVS1"
	      DstPort		      RConn1
	    }
	    Line {
	      LineType		      "Connection"
	      SrcBlock		      "-"
	      SrcPort		      RConn1
	      Points		      [0, 65; -130, 0]
	      DstBlock		      "CVS2"
	      DstPort		      LConn1
	    }
	    Line {
	      SrcBlock		      "Gain1"
	      SrcPort		      1
	      Points		      [15, 0]
	      Branch {
		DstBlock		"CVS1"
		DstPort			1
	      }
	      Branch {
		Points			[0, 115]
		DstBlock		"CVS2"
		DstPort			1
	      }
	    }
	    Annotation {
	      Name		      "1V in produces 1V (differential) out."
	      Position		      [190, 291]
	    }
	  }
	}
	Block {
	  BlockType		  Gain
	  Name			  "Gain1"
	  Position		  [220, 493, 255, 527]
	  Orientation		  "left"
	  Gain			  "-1"
	}
	Block {
	  BlockType		  Gain
	  Name			  "Gain2"
	  Position		  [455, 440, 485, 470]
	  Orientation		  "left"
	  Gain			  "-2"
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Invert"
	  Ports			  [1, 1]
	  Position		  [640, 112, 685, 138]
	  TreatAsAtomicUnit	  off
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  System {
	    Name		    "Invert"
	    Location		    [438, 173, 818, 383]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [15, 98, 45, 112]
	      Port		      "1"
	      IconDisplay	      "Port number"
	      LatchInput	      off
	    }
	    Block {
	      BlockType		      DataTypeConversion
	      Name		      "Data Type Conversion"
	      Position		      [75, 91, 130, 119]
	      OutDataTypeMode	      "boolean"
	    }
	    Block {
	      BlockType		      DataTypeConversion
	      Name		      "Data Type Conversion1"
	      Position		      [230, 91, 285, 119]
	      OutDataTypeMode	      "double"
	    }
	    Block {
	      BlockType		      Logic
	      Name		      "Logical\nOperator"
	      Ports		      [1, 1]
	      Position		      [175, 90, 205, 120]
	      NamePlacement	      "alternate"
	      Operator		      "NOT"
	      AllPortsSameDT	      off
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [310, 97, 340, 113]
	      IconDisplay	      "Port number"
	      BusOutputAsStruct	      off
	    }
	    Line {
	      SrcBlock		      "Data Type Conversion"
	      SrcPort		      1
	      DstBlock		      "Logical\nOperator"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Logical\nOperator"
	      SrcPort		      1
	      DstBlock		      "Data Type Conversion1"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Data Type Conversion"
	      DstPort		      1
	    }
	    Line {
	      SrcBlock		      "Data Type Conversion1"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  Mux
	  Name			  "Mux"
	  Ports			  [3, 1]
	  Position		  [805, 76, 815, 134]
	  ShowName		  off
	  Inputs		  "3"
	  DisplayOption		  "bar"
	}
	Block {
	  BlockType		  Mux
	  Name			  "Mux1"
	  Ports			  [5, 1]
	  Position		  [880, 168, 890, 262]
	  ShowName		  off
	  Inputs		  "5"
	  DisplayOption		  "bar"
	}
	Block {
	  BlockType		  DiscretePulseGenerator
	  Name			  "S&H strobe"
	  Ports			  [0, 1]
	  Position		  [35, 33, 80, 67]
	  PulseType		  "Time based"
	  Period		  "1/Fs"
	  PulseWidth		  "0.01"
	  PhaseDelay		  "0.5005/Fs"
	  Port {
	    PortNumber		    1
	    Name		    "Clk_0"
	    RTWStorageClass	    "Auto"
	    DataLoggingNameMode	    "SignalName"
	    ShowSigGenPortName	    on
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Sampler"
	  Ports			  [1, 1, 1]
	  Position		  [675, 324, 725, 366]
	  TreatAsAtomicUnit	  off
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  System {
	    Name		    "Sampler"
	    Location		    [616, 211, 1100, 392]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "In1"
	      Position		      [110, 103, 140, 117]
	      Port		      "1"
	      IconDisplay	      "Port number"
	      LatchInput	      off
	    }
	    Block {
	      BlockType		      EnablePort
	      Name		      "Enable"
	      Ports		      []
	      Position		      [230, 50, 250, 70]
	    }
	    Block {
	      BlockType		      Outport
	      Name		      "Out1"
	      Position		      [360, 103, 390, 117]
	      IconDisplay	      "Port number"
	      BusOutputAsStruct	      off
	      InitialOutput	      "[0]"
	    }
	    Line {
	      SrcBlock		      "In1"
	      SrcPort		      1
	      DstBlock		      "Out1"
	      DstPort		      1
	    }
	  }
	}
	Block {
	  BlockType		  SubSystem
	  Name			  "Summer + Integrator 1"
	  Ports			  [3, 1, 0, 0, 0, 4, 2]
	  Position		  [190, 238, 325, 402]
	  TreatAsAtomicUnit	  off
	  MinAlgLoopOccurrences	  off
	  RTWSystemCode		  "Auto"
	  System {
	    Name		    "Summer + Integrator 1"
	    Location		    [331, 301, 1103, 811]
	    Open		    off
	    ModelBrowserVisibility  off
	    ModelBrowserWidth	    200
	    ScreenColor		    "white"
	    PaperOrientation	    "landscape"
	    PaperPositionMode	    "auto"
	    PaperType		    "usletter"
	    PaperUnits		    "inches"
	    ZoomFactor		    "100"
	    Block {
	      BlockType		      Inport
	      Name		      "Clk_1"
	      Position		      [95, 103, 125, 117]
	      Port		      "1"
	      IconDisplay	      "Port number"
	      LatchInput	      off
	    }
	    Block {
	      BlockType		      Inport
	      Name		      "Clk_2"
	      Position		      [95, 163, 125, 177]
	      Port		      "2"
	      IconDisplay	      "Port number"
	      LatchInput	      off
	    }
	    Block {
	      BlockType		      Inport

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