disp.vhd

张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY DISP IS
    PORT(
        DIN    : IN    STD_LOGIC_VECTOR(2 DOWNTO 0);
        SEG7: OUT    STD_LOGIC_VECTOR(7 DOWNTO 0));
END DISP;
ARCHITECTURE DISP_6 OF DISP IS
BEGIN
    SEG7 <= "00000110" WHEN DIN = "000" ELSE -- 1
            "01011011" WHEN DIN = "001" ELSE -- 2
            "01001111" WHEN DIN = "010" ELSE -- 3
            "01100110" WHEN DIN = "011" ELSE -- 4
            "01101101" WHEN DIN = "100" ELSE -- 5
            "01111101" WHEN DIN = "101" ELSE -- 6
            "00000000";
END DISP_6;