sw.vhd

张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY SW IS
    PORT(
        SW    : IN    STD_LOGIC_VECTOR(2 DOWNTO 0);
        CTRL: OUT    STD_LOGIC_VECTOR(5 DOWNTO 0));
END SW;
ARCHITECTURE CTRL OF SW IS
BEGIN
    CTRL <= "100000" WHEN SW = "000" ELSE     --1
            "010000" WHEN SW = "001" ELSE     --2
            "001000" WHEN SW = "010" ELSE     --3
            "000100" WHEN SW = "011" ELSE     --4
            "000010" WHEN SW = "100" ELSE     --5
            "000001" WHEN SW = "101" ELSE     --6
            "000000";
END CTRL;