test_disp123456.vhdtst

张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘

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-- VHDL Testbench for DISP123456
-- 2003 5 29 10 49 10
-- Created by "EditVHDL"
-- "Copyright (c) 2002 Altium Limited"
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Library IEEE;
Use     IEEE.std_logic_1164.all;
Use     IEEE.std_logic_textio.all;
Use     STD.textio.all;
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entity TestDISP123456 is
end TestDISP123456;
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architecture stimulus of TestDISP123456 is
    file RESULTS: TEXT open WRITE_MODE is "results.txt";
    procedure WRITE_RESULTS(
        CLK: std_logic;
        CTRL: std_logic_vector(5 downto 0);
        SEG7: std_logic_vector(7 downto 0)
    ) is
        variable l_out : line;
    begin
        write(l_out, now, right, 15);
        write(l_out, CLK, right, 2);
        write(l_out, CTRL, right, 7);
        write(l_out, SEG7, right, 9);
        writeline(RESULTS, l_out);
    end procedure;

    component DISP123456
        port (
            CLK: in std_logic;
            CTRL: out std_logic_vector(5 downto 0);
            SEG7: out std_logic_vector(7 downto 0)
        );
    end component;

    signal CLK: std_logic;
    signal CTRL: std_logic_vector(5 downto 0);
    signal SEG7: std_logic_vector(7 downto 0);

begin
    DUT :DISP123456 port map (
        CLK => CLK,
        CTRL => CTRL,
        SEG7 => SEG7
    );

    STIMULUS0:process
    begin
        -- insert stimulus here
       CLK <= '1';
       wait for 10 ns;
       CLK <= '0';
       wait for 10 ns;
        --wait;
    end process;

    WRITE_RESULTS(
        CLK,
        CTRL,
        SEG7
    );

end architecture;
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