cnt3b.vhd

来自「张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘」· VHDL 代码 · 共 27 行

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY CNT3B IS
    PORT(
        CLK    : IN    STD_LOGIC;
        Q   : OUT    STD_LOGIC_VECTOR(2 DOWNTO 0)
        );
END CNT3B;
ARCHITECTURE CNT OF CNT3B IS
SIGNAL TMP : STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK='1') THEN
    IF TMP < 5 THEN
        TMP <= TMP+1;
        ELSE
        TMP <="000";
        END IF;
    END IF;
    Q <= TMP;
    END PROCESS;
END CNT;