disp123456.prjfpg

张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘

[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=0
OutputPath=
ChannelDesignatorFormatString=$Component_$RoomName
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=0
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0
[Document1]
DocumentPath=Bufgs.vhdmdl
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1
[Document2]
DocumentPath=Test_DISP123456.VHDTST
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1
[Document3]
DocumentPath=DISP123456.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1
[Document4]
DocumentPath=sw.vhd
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1
[Document5]
DocumentPath=disp.vhd
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1
[Document6]
DocumentPath=cnt3b.vhd
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1
[Document7]
DocumentPath=DISP123456.SCHLIB
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1
[GeneratedDocument1]
DocumentPath=ProjectOutputs\DISP123456.SO
[GeneratedDocument2]
DocumentPath=ProjectOutputs\DISP123456.VHD
[Generic_VHDLSynthesis]
InsertIOBuffers=True
InferMacrocell=True
MapSynopsysLibrary=True
MapNumericLibrary=False
SettingsModified=True
Entity=
Architecture=
Vendor=altera
Family=
[Generic_VHDLSimulationWatches]
WatchName0=CLK
WatchEnable0=True
WatchWave0=True
WatchName1=CTRL
WatchEnable1=True
WatchWave1=True
WatchName2=SEG7
WatchEnable2=True
WatchWave2=True
[Generic_VHDLSimulation]
NoIEEE=False
VHDL93=True
TopLevelEntity=TESTDISP123456
TopLevelArchitecture=
TopLevelUnit=Test_DISP123456.VHDTST
RunToTime=100000000
SDFInstance=
SDFFileName=
SDFOptimization=1
SettingsModified=False
TimeStep=1000000000
TimeUnits=ns
RunToUnits=ns
[OutputGroup1]
Name=Netlist Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=ProtelNetlist
OutputName1=Protel
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
OutputType2=VHDL
OutputName2=VHDL File
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
Configuration2_Name1=OutputConfigurationParameter1
Configuration2_Item1=Crossprobe=False|EnableAttributes=True|Record=VHDLView|SingleFile=True
OutputType3=XSpiceNetlist
OutputName3=XSpice Netlist
OutputDocumentPath3=
OutputEnabled3=1
OutputDefault3=0
OutputType4=PLDNetList
OutputName4=CUPL PLD
OutputDocumentPath4=
OutputEnabled4=1
OutputDefault4=0
Configuration4_Name1=OutputConfigurationParameter1
Configuration4_Item1=Record=AdvPLDSettings|PldMinimizeMethod=1|PldDeviceName=Virtual|PldDeviceLibrary=Virtual|PldSecureDevice=False|PldDeactivateUnusedORTerms=False|PldSuppressProductTermsMerging=True|PldOneHotBitStateMachine=False|PldOutputOptionAscii=False|PldOutputOptionAbsolute=True|PldOutputOptionErrorList=True|PldOutputOptionBerkelyPla=False|PldOutputOptionExpandedMacro=False|PldOutputOptionEdif=False|PldOutputOptionHex=False|PldOutputOptionJedec=True|PldOutputOptionPalasm=False|PldOutputOptionPdif=False|PldOutputOptionXnf=False|PldOutputOptionFusePlotInDoc=True|PldOutputOptionEquationsInDoc=True|PldBestForPolarity=False|PldDeMorgan=False|PldKeepXOR=False|PldProductTermSharing=False|UseVirtualDevice=False|UsePinNode=True
OutputType5=EDIF
OutputName5=EDIF for PCB
OutputDocumentPath5=
OutputEnabled5=1
OutputDefault5=0
Configuration5_Name1=OutputConfigurationParameter1
Configuration5_Item1=NetlistVersion=0|Record=EdifView
OutputType6=EDIFfpga
OutputName6=EDIF for FPGA
OutputDocumentPath6=
OutputEnabled6=1
OutputDefault6=0
OutputType7=MultiWire
OutputName7=MultiWire
OutputDocumentPath7=
OutputEnabled7=1
OutputDefault7=0
[OutputGroup2]
Name=Simulator Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=AdvSimNetlist
OutputName1=Mixed Sim
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
OutputType2=PLDNetListSim
OutputName2=CUPL PLD
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
[OutputGroup3]
Name=Documentation Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=Composite
OutputName1=Composite Drawing
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
PageOptions1=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType2=PCB Print
OutputName2=PCB Prints
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
PageOptions2=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType3=Schematic Print
OutputName3=Schematic Prints
OutputDocumentPath3=
OutputEnabled3=1
OutputDefault3=0
PageOptions3=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
[OutputGroup4]
Name=Assembly Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=Assembly
OutputName1=Assembly Drawings
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
PageOptions1=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType2=Pick Place
OutputName2=Generates pick and place files
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
[OutputGroup5]
Name=Fabrication Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=CompositeDrill
OutputName1=Composite Drill Drawing
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
PageOptions1=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType2=Drill
OutputName2=Drill Drawing/Guides
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
PageOptions2=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType3=Final
OutputName3=Final Artwork Prints
OutputDocumentPath3=
OutputEnabled3=1
OutputDefault3=0
PageOptions3=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType4=Gerber
OutputName4=Gerber Files
OutputDocumentPath4=
OutputEnabled4=1
OutputDefault4=0
OutputType5=Mask
OutputName5=Solder/Paste Mask Prints
OutputDocumentPath5=
OutputEnabled5=1
OutputDefault5=0
PageOptions5=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType6=NC Drill
OutputName6=NC Drill Files
OutputDocumentPath6=
OutputEnabled6=1
OutputDefault6=0
OutputType7=ODB
OutputName7=ODB++ Files
OutputDocumentPath7=
OutputEnabled7=1
OutputDefault7=0
OutputType8=Plane
OutputName8=Power-Plane Prints
OutputDocumentPath8=
OutputEnabled8=1
OutputDefault8=0
PageOptions8=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=1|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=2|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType9=Test Points
OutputName9=Test Point Report
OutputDocumentPath9=
OutputEnabled9=1
OutputDefault9=0
[OutputGroup6]
Name=Report Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=BOM_PartType
OutputName1=Bill of Materials
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
OutputType2=ComponentCrossReference
OutputName2=Component Cross Reference Report
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
OutputType3=ReportHierarchy
OutputName3=Report Project Hierarchy
OutputDocumentPath3=
OutputEnabled3=1
OutputDefault3=0
OutputType4=SimpleBOM
OutputName4=Simple BOM
OutputDocumentPath4=
OutputEnabled4=1
OutputDefault4=0
[OutputGroup7]
Name=Other Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
[Modification Levels]
Type1=1
Type2=1
Type3=1
Type4=1
Type5=1
Type6=1
Type7=1
Type8=1
Type9=1
Type10=1
Type11=1
Type12=1
Type13=1
Type14=1
Type15=1
Type16=1
Type17=1
Type18=1
Type19=1
Type20=1
Type21=1
Type22=1
Type23=1
Type24=1
Type25=1
Type26=1
Type27=1
Type28=1
Type29=1
Type30=1
Type31=1
Type32=1
Type33=1
Type34=1
Type35=1
Type36=1
Type37=1
Type38=1
Type39=1
Type40=1
Type41=1
Type42=1
Type43=1
Type44=1
Type45=1
[Difference Levels]
Type1=1
Type2=1
Type3=1
Type4=1
Type5=1
Type6=1
Type7=1
Type8=1
Type9=1
Type10=1
Type11=1
Type12=1
Type13=1
Type14=1
Type15=1
Type16=1
Type17=1
Type18=1
Type19=1
Type20=1
Type21=1
Type22=1
Type23=1
Type24=1
Type25=1
[Electrical Rules Check]
Type1=1
Type2=1
Type3=2
Type4=1
Type5=2
Type6=2
Type7=1
Type8=1
Type9=1
Type10=1
Type11=2
Type12=2
Type13=2
Type14=0
Type15=1
Type16=1
Type17=1
Type18=1
Type19=1
Type20=1
Type21=1
Type22=1
Type23=1
Type24=1
Type25=2
Type26=2
Type27=2
Type28=1
Type29=1
Type30=1
Type31=1
Type32=2
Type33=2
Type34=2
Type35=1
Type36=2
Type37=1
Type38=2
Type39=2
Type40=2
Type41=0
Type42=2
Type43=1
Type44=1
Type45=2
Type46=1
Type47=2
Type48=2
Type49=1
Type50=2
Type51=1
Type52=1
Type53=1
Type54=1
Type55=1
Type56=2
Type57=1
Type58=1
[ERC Connection Matrix]
L1=NNNNNNNNNNNWNNNWW
L2=NNWNNNNWWWNWNWNWN
L3=NWEENEEEENEWNEEWN
L4=NNENNNWEENNWNENWN
L5=NNNNNNNNNNNNNNNNN
L6=NNENNNNEENNWNENWN
L7=NNEWNNWEENNWNENWN
L8=NWEENEENEEENNEENN
L9=NWEENEEEENEWNEEWW
L10=NWNNNNNENNEWNNEWN
L11=NNENNNNEEENWNENWN
L12=WWWWNWWNWWWNWWWNN
L13=NNNNNNNNNNNWNNNWW
L14=NWEENEEEENEWNEEWW
L15=NNENNNNEEENWNENWW
L16=WWWWNWWNWWWNWWWNW
L17=WNNNNNNNWNNNWWWWN
[Annotate]
SortOrder=3
MatchParameter1=Comment
[HighlightMethod]
Zoom=1
Select=0
Filter=1
Graph=0
IncludePower=0
[DisplayedObject]
Pin=1
NetLabel=1
Port=1
CrossSheet=1
SheetEntry=1
SheetSymbol=1
Part=0
Component=0
Net=0
Bus=0
Line=0
[LibraryUpdateOptions]
SelectedOnly=0
FullReplace=1
DoGraphics=1
DoParameters=1
DoModels=1
AddParameters=0
RemoveParameters=0
AddModels=1
RemoveModels=1
UpdateCurrentModels=1
[DatabaseUpdateOptions]
SelectedOnly=0