disp123456.vhd

张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘

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-- VHDL DISP123456
-- 2003 6 5 3 26 57
-- Created By "nVisage DXP"
-- "Copyright (c) 2002 Altium Limited"
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-- VHDL DISP123456
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Library IEEE;
Use     IEEE.std_logic_1164.all;

entity DISP123456 is
  port
  (
    CLK  : in  STD_LOGIC;    -- ObjectKind=Port|PrimaryId=CLK
    CTRL : out STD_LOGIC_VECTOR(5 downto 0);    -- ObjectKind=Port|PrimaryId=CTRL
    SEG7 : out STD_LOGIC_VECTOR(7 downto 0)    -- ObjectKind=Port|PrimaryId=SEG7
  );

  attribute PART_NAME : string;
  attribute PART_NAME of DISP123456 : entity is "EPF10K10TC144-4";


begin

end DISP123456;
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architecture structure of DISP123456 is
   component BUFGS    -- ObjectKind=Component|PrimaryId=U1
      port
      (
        I : in  STD_LOGIC;    -- ObjectKind=Pin|PrimaryId=U1-I
        O : out STD_LOGIC    -- ObjectKind=Pin|PrimaryId=U1-O
      );
   end component;

   component CNT3B    -- ObjectKind=SheetSymbol|PrimaryId=U2
      port
      (
        CLK : in  STD_LOGIC;    -- ObjectKind=Sheet Entry|PrimaryId=U2-CLK
        Q   : out STD_LOGIC_VECTOR(2 downto 0)    -- ObjectKind=Sheet Entry|PrimaryId=U2-Q
      );
   end component;

   component DISP    -- ObjectKind=SheetSymbol|PrimaryId=U3
      port
      (
        DIN  : in  STD_LOGIC_VECTOR(2 downto 0);    -- ObjectKind=Sheet Entry|PrimaryId=U3-DIN
        SEG7 : out STD_LOGIC_VECTOR(7 downto 0)    -- ObjectKind=Sheet Entry|PrimaryId=U3-SEG7
      );
   end component;

   component SW    -- ObjectKind=SheetSymbol|PrimaryId=U4
      port
      (
        CTRL : out STD_LOGIC_VECTOR(5 downto 0);    -- ObjectKind=Sheet Entry|PrimaryId=U4-CTRL
        SW   : in  STD_LOGIC_VECTOR(2 downto 0)    -- ObjectKind=Sheet Entry|PrimaryId=U4-SW
      );
   end component;

   signal N00019 : STD_LOGIC;    -- ObjectKind=Netlabel|PrimaryId=N00019
   signal N00001 : STD_LOGIC_VECTOR(5 downto 0);    -- ObjectKind=Netlabel|PrimaryId=N00001
   signal N00022 : STD_LOGIC_VECTOR(7 downto 0);    -- ObjectKind=Netlabel|PrimaryId=N00022
   signal N00020 : STD_LOGIC;    -- ObjectKind=Netlabel|PrimaryId=N00020
   signal N00021 : STD_LOGIC_VECTOR(2 downto 0);    -- ObjectKind=Netlabel|PrimaryId=N00021


   attribute Component_Kind : string;
   attribute Component_Kind of U1 : label is "Standard";

   attribute Library_Name : string;
   attribute Library_Name of U1 : label is "DISP123456.SCHLIB";

   attribute Library_Reference : string;
   attribute Library_Reference of U1 : label is "BUFGS";

   attribute VHDL : string;
   attribute VHDL of U1 : label is "BUFGS";


begin

   U1 : BUFGS    -- ObjectKind=Component|PrimaryId=U1
     port map
     (
       I                => N00019,    -- ObjectKind=Pin|PrimaryId=U1-I
       O                => N00020    -- ObjectKind=Pin|PrimaryId=U1-O
     );

   U2 : CNT3B    -- ObjectKind=SheetSymbol|PrimaryId=U2
     port map
     (
       CLK              => N00020,    -- ObjectKind=Sheet Entry|PrimaryId=cnt3b.vhd-CLK
       Q(2 downto 0)    => N00021(2 downto 0)    -- ObjectKind=Sheet Entry|PrimaryId=cnt3b.vhd-Q[2..0]
     );

   U3 : DISP    -- ObjectKind=SheetSymbol|PrimaryId=U3
     port map
     (
       DIN(2 downto 0)  => N00021(2 downto 0),    -- ObjectKind=Sheet Entry|PrimaryId=disp.vhd-DIN[2..0]
       SEG7(7 downto 0) => N00022(7 downto 0)    -- ObjectKind=Sheet Entry|PrimaryId=disp.vhd-SEG7[7..0]
     );

   U4 : SW    -- ObjectKind=SheetSymbol|PrimaryId=U4
     port map
     (
       CTRL(5 downto 0) => N00001(5 downto 0),    -- ObjectKind=Sheet Entry|PrimaryId=sw.vhd-CTRL[5..0]
       SW(2 downto 0)   => N00021(2 downto 0)    -- ObjectKind=Sheet Entry|PrimaryId=sw.vhd-SW[2..0]
     );

   N00019           <= CLK;    -- ObjectKind=Port|PrimaryId=CLK
   CTRL(5 downto 0) <= N00001(5 downto 0);    -- ObjectKind=Port|PrimaryId=CTRL
   SEG7(7 downto 0) <= N00022(7 downto 0);    -- ObjectKind=Port|PrimaryId=SEG7


end structure;
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