bcd.vhd

张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘

------------------------------------------------------------
-- VHDL BCD.PRJFPG
-- 2003 7 9 10 0 20
-- Created By "nVisage DXP"
-- "Copyright (c) 2002 Altium Limited"
------------------------------------------------------------

------------------------------------------------------------
-- VHDL BCD
------------------------------------------------------------


-- BCD.VHD
-- Binary Coded Decimal Counter (0-9) with RCO

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use ieee.std_logic_unsigned.all;


--------------------BCD-----------------------------------------
entity BCD is
  port(CLEAR,CLOCK,ENABLE: in  std_logic;
          RCO:             out std_logic;
          OCD:             out std_logic_vector(3 downto 0));
end;

architecture RTL of BCD is
  signal CURRENT_COUNT,NEXT_COUNT: std_logic_vector(3 downto 0);
begin

  REGISTER_BLOCK: process (CLEAR,CLOCK,NEXT_COUNT)
  begin
     if (CLEAR='1') then
        CURRENT_COUNT<=x"0";
     elsif (CLOCK='1' and CLOCK'event) then
        CURRENT_COUNT<=NEXT_COUNT;
     end if;
  end process;

-- Binary Coded Decimal generator combinational logic block
  BCD_GENERATOR: process (CURRENT_COUNT,ENABLE)
  begin
     if (CURRENT_COUNT=x"9") and (ENABLE='1') then
        NEXT_COUNT<=x"0";
        RCO <= '1';
     else
        if (ENABLE='1') then
           NEXT_COUNT <= CURRENT_COUNT + 1;
        else
           NEXT_COUNT <= CURRENT_COUNT;
        end if;
        RCO <= '0';
     end if;
  end process;
  OCD <= CURRENT_COUNT;

end;
---------------------------------------------------------------------

---------------------------------------------------------------------
------------------------------------------------------------
-- VHDL BCD8
------------------------------------------------------------

Library IEEE;
Use     IEEE.std_logic_1164.all;

  -- rtl_synthesis off
  Library BCD_LIB;
  Use BCD_LIB.all ;
  -- rtl_synthesis on

entity BCD8 is
  port
  (
    CLEAR  : in  STD_LOGIC;    -- ObjectKind=Port|PrimaryId=CLEAR
    CLOCK  : in  STD_LOGIC;    -- ObjectKind=Port|PrimaryId=CLOCK
    ENABLE : in  STD_LOGIC;    -- ObjectKind=Port|PrimaryId=ENABLE
    LOWER  : out STD_LOGIC_VECTOR(3 downto 0);    -- ObjectKind=Port|PrimaryId=LOWER
    PARITY : out STD_LOGIC;    -- ObjectKind=Port|PrimaryId=PARITY
    UPPER  : out STD_LOGIC_VECTOR(3 downto 0);    -- ObjectKind=Port|PrimaryId=UPPER
    URCO   : out STD_LOGIC    -- ObjectKind=Port|PrimaryId=URCO
  );

begin

end BCD8;
------------------------------------------------------------

------------------------------------------------------------
architecture structure of BCD8 is
   component BUFGS    -- ObjectKind=Component|PrimaryId=U1
      port
      (
        I : in  STD_LOGIC;    -- ObjectKind=Pin|PrimaryId=U1-I
        O : out STD_LOGIC    -- ObjectKind=Pin|PrimaryId=U1-O
      );
   end component;

   component PARITYC    -- ObjectKind=Component|PrimaryId=U2
      port
      (
        L : in  STD_LOGIC_VECTOR(3 downto 0);    -- ObjectKind=Pin|PrimaryId=U2-L
        P : out STD_LOGIC;    -- ObjectKind=Pin|PrimaryId=U2-P
        U : in  STD_LOGIC_VECTOR(3 downto 0)    -- ObjectKind=Pin|PrimaryId=U2-U
      );
   end component;

   component BCD    -- ObjectKind=SheetSymbol|PrimaryId=H1
      port
      (
        CLEAR  : in  STD_LOGIC;    -- ObjectKind=Sheet Entry|PrimaryId=H1-CLEAR
        CLOCK  : in  STD_LOGIC;    -- ObjectKind=Sheet Entry|PrimaryId=H1-CLOCK
        ENABLE : in  STD_LOGIC;    -- ObjectKind=Sheet Entry|PrimaryId=H1-ENABLE
        OCD    : out STD_LOGIC_VECTOR(3 downto 0);    -- ObjectKind=Sheet Entry|PrimaryId=H1-OCD
        RCO    : out STD_LOGIC    -- ObjectKind=Sheet Entry|PrimaryId=H1-RCO
      );
   end component;

   signal N00001 : STD_LOGIC;    -- ObjectKind=Netlabel|PrimaryId=N00001
   signal N00012 : STD_LOGIC;    -- ObjectKind=Netlabel|PrimaryId=N00012
   signal N00002 : STD_LOGIC;    -- ObjectKind=Netlabel|PrimaryId=N00002
   signal S2     : STD_LOGIC_VECTOR(3 downto 0);    -- ObjectKind=Netlabel|PrimaryId=S2
   signal N00014 : STD_LOGIC;    -- ObjectKind=Netlabel|PrimaryId=N00014
   signal S1     : STD_LOGIC_VECTOR(3 downto 0);    -- ObjectKind=Netlabel|PrimaryId=S1
   signal N00015 : STD_LOGIC;    -- ObjectKind=Netlabel|PrimaryId=N00015
   signal N00013 : STD_LOGIC;    -- ObjectKind=Netlabel|PrimaryId=N00013
   signal LRCO   : STD_LOGIC;    -- ObjectKind=Netlabel|PrimaryId=LRCO


   attribute Component_Kind : string;
   attribute Component_Kind of U1 : label is "Standard";
   attribute Component_Kind of U2 : label is "Standard";

   attribute Library_Name : string;
   attribute Library_Name of U1 : label is "BCD.SCHLIB";
   attribute Library_Name of U2 : label is "BCD.SCHLIB";

   attribute Library_Reference : string;
   attribute Library_Reference of U1 : label is "BUFGS";
   attribute Library_Reference of U2 : label is "PARITYC";

   attribute VHDL : string;
   attribute VHDL of U1 : label is "BUFGS";


begin

   U1 : BUFGS    -- ObjectKind=Component|PrimaryId=U1
     port map
     (
       I                 => N00012,    -- ObjectKind=Pin|PrimaryId=U1-I
       O                 => N00013    -- ObjectKind=Pin|PrimaryId=U1-O
     );

   U2 : PARITYC    -- ObjectKind=Component|PrimaryId=U2
     port map
     (
       L(3 downto 0)     => S2(3 downto 0),    -- ObjectKind=Pin|PrimaryId=U2-L[3..0]
       P                 => N00014,    -- ObjectKind=Pin|PrimaryId=U2-P
       U(3 downto 0)     => S1(3 downto 0)    -- ObjectKind=Pin|PrimaryId=U2-U[3..0]
     );

   H1 : BCD    -- ObjectKind=SheetSymbol|PrimaryId=H1
     port map
     (
       CLEAR             => N00001,    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-CLEAR
       CLOCK             => N00013,    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-CLOCK
       ENABLE            => N00002,    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-ENABLE
       OCD(3 downto 0)   => S2(3 downto 0),    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-OCD[3..0]
       RCO               => LRCO    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-RCO
     );

   H2 : BCD    -- ObjectKind=SheetSymbol|PrimaryId=H2
     port map
     (
       CLEAR             => N00001,    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-CLEAR
       CLOCK             => N00013,    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-CLOCK
       ENABLE            => LRCO,    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-ENABLE
       OCD(3 downto 0)   => S1(3 downto 0),    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-OCD[3..0]
       RCO               => N00015    -- ObjectKind=Sheet Entry|PrimaryId=BCD.Vhd-RCO
     );

   N00001            <= CLEAR;    -- ObjectKind=Port|PrimaryId=CLEAR
   N00012            <= CLOCK;    -- ObjectKind=Port|PrimaryId=CLOCK
   N00002            <= ENABLE;    -- ObjectKind=Port|PrimaryId=ENABLE
   LOWER(3 downto 0) <= S2(3 downto 0);    -- ObjectKind=Port|PrimaryId=LOWER
   PARITY            <= N00014;    -- ObjectKind=Port|PrimaryId=PARITY
   UPPER(3 downto 0) <= S1(3 downto 0);    -- ObjectKind=Port|PrimaryId=UPPER
   URCO              <= N00015;    -- ObjectKind=Port|PrimaryId=URCO


end structure;
------------------------------------------------------------

------------------------------------------------------------
-- VHDL PARITY
------------------------------------------------------------

Library IEEE;
Use     IEEE.std_logic_1164.all;
Use     WORK.utility.all;

entity PARITYC is
  port
  (
    L   : in STD_LOGIC_VECTOR(3 downto 0);
    U   : in STD_LOGIC_VECTOR(3 downto 0);
    P     : out STD_LOGIC
  );
end PARITYC;

architecture PARITY_Arch of PARITYC is

signal VTC : STD_LOGIC_VECTOR(7 downto 0);

begin
    VTC(7 downto 4) <= U;
    VTC(3 downto 0) <= L;

    P <= fparity(VTC);

end PARITY_Arch;
------------------------------------------------------------
-- VHDL UTILITY
------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package UTILITY IS

    function fparity (vtctp : std_logic_vector) return std_logic;

end Utility;

library IEEE;
use IEEE.STD_LOGIC_1164.all;

package body UTILITY is

    function fparity (vtctp : std_logic_vector) return std_logic is
        variable respar : std_logic;
    begin
        respar := '0';
        for i in 0 to vtctp'length - 1 loop
            if vtctp(i) = '1' then
                respar := not respar;
            end if;
        end loop;
        return respar;
    end function fparity;

end package body UTILITY;