peak detector - multi channel (1).~prjpcb

张义和《protel DXP 电路设计大全》中国铁道出版社 随书光盘

[Design]
Version=1.0
HierarchyMode=0
ChannelRoomNamingStyle=4
OutputPath=
ChannelDesignatorFormatString=$Component_$ChannelPrefix$ChannelIndex
ChannelRoomLevelSeperator=_
OpenOutputs=1
ArchiveProject=0
TimestampOutput=0
SeparateFolders=1
AllowPortNetNames=0
AllowSheetEntryNetNames=1
AppendSheetNumberToLocalNets=0

[Document1]
DocumentPath=Bank.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1

[Document2]
DocumentPath=Peak Detector - channel.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1

[Document3]
DocumentPath=Peak Detector.SchDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1

[Document4]
DocumentPath=Peak Detector With Banking.PcbDoc
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1

[Document5]
DocumentPath=Peak Detector With Banking.PcbLib
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1

[Document6]
DocumentPath=Default Assembly Outputs.OutJob
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1

[Document7]
DocumentPath=Default Fabrication Outputs.OutJob
AnnotationEnabled=1
AnnotateStartValue=1
AnnotateSuffix=
DoLibraryUpdate=1
DoDatabaseUpdate=1

[SearchPath1]
Path=*.*
IncludeSubFolders=1

[OutputGroup1]
Name=Netlist Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=EDIF
OutputName1=EDIF for PCB
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
OutputType2=EDIFfpga
OutputName2=EDIF for FPGA
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
OutputType3=MultiWire
OutputName3=MultiWire
OutputDocumentPath3=
OutputEnabled3=1
OutputDefault3=0
OutputType4=PLDNetList
OutputName4=CUPL PLD
OutputDocumentPath4=
OutputEnabled4=1
OutputDefault4=0
OutputType5=ProtelNetlist
OutputName5=Protel
OutputDocumentPath5=
OutputEnabled5=1
OutputDefault5=0
OutputType6=VHDL
OutputName6=VHDL File
OutputDocumentPath6=
OutputEnabled6=1
OutputDefault6=0
OutputType7=XSpiceNetlist
OutputName7=XSpice Netlist
OutputDocumentPath7=
OutputEnabled7=1
OutputDefault7=0

[OutputGroup2]
Name=Simulator Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=AdvSimNetlist
OutputName1=Mixed Sim
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
OutputType2=PLDNetListSim
OutputName2=CUPL PLD
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
OutputType3=SignalIntegrity
OutputName3=Signal Integrity
OutputDocumentPath3=
OutputEnabled3=1
OutputDefault3=0

[OutputGroup3]
Name=Documentation Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=Composite
OutputName1=Composite Drawing
OutputDocumentPath1=
OutputEnabled1=1
OutputDefault1=0
PageOptions1=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=1|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType2=PCB Print
OutputName2=PCB Prints
OutputDocumentPath2=
OutputEnabled2=1
OutputDefault2=0
PageOptions2=Record=PageOptions|SelectedOnly=False|CenterHorizontal=True|CenterVertical=True|PrintScale=1.00|XCorrection=1.00|YCorrection=1.00|PrintKind=0|BorderSize=5000000|LeftOffset=0|BottomOffset=0|Orientation=1|PaperLength=1000|PaperWidth=1000|Scale=100|PaperSource=7|PrintQuality=-4|MediaType=1|DitherType=10|PaperKind=A4
OutputType3=Schematic Print
OutputName3=Schematic Prints
OutputDocumentPath3=
OutputEnabled3=1
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[OutputGroup4]
Name=Assembly Outputs
Description=
PrinterOptions=Record=PrinterOptions|Copies=1|Duplex=1|TrueTypeOptions=3|Collate=1|PrintWhat=1
OutputType1=Pick Place
OutputName1=Generates pick and place files
OutputDocumentPath1=