📄 m_usiu.h
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VUINT32 IRQ3:1;
VUINT32 LVL3:1;
VUINT32 IMBIRQ12:1;
VUINT32 IMBIRQ13:1;
VUINT32 IMBIRQ14:1;
VUINT32 IMBIRQ15:1;
VUINT32 IRQ4:1;
VUINT32 LVL4:1;
VUINT32 IMBIRQ16:1;
VUINT32 IMBIRQ17:1;
VUINT32 IMBIRQ18:1;
VUINT32 IMBIRQ19:1;
VUINT32 IRQ5:1;
VUINT32 LVL5:1;
} B;
} SIMASK2;
union {
VUINT32 R;
struct {
VUINT32 IMBIRQ20:1;
VUINT32 IMBIRQ21:1;
VUINT32 IMBIRQ22:1;
VUINT32 IMBIRQ23:1;
VUINT32 IRQ6:1;
VUINT32 LVL6:1;
VUINT32 IMBIRQ24:1;
VUINT32 IMBIRQ25:1;
VUINT32 IMBIRQ26:1;
VUINT32 IMBIRQ27:1;
VUINT32 IRQ7:1;
VUINT32 LVL7:1;
VUINT32 IMBIRQ28:1;
VUINT32 IMBIRQ29:1;
VUINT32 IMBIRQ30:1;
VUINT32 IMBIRQ31:1;
VUINT32:16;
} B;
} SIMASK3;
union {
VUINT32 R;
struct {
VUINT32 IRQ0:1;
VUINT32 LVL0:1;
VUINT32 IMBIRQ0:1;
VUINT32 IMBIRQ1:1;
VUINT32 IMBIRQ2:1;
VUINT32 IMBIRQ3:1;
VUINT32 IRQ1:1;
VUINT32 LVL1:1;
VUINT32 IMBIRQ4:1;
VUINT32 IMBIRQ5:1;
VUINT32 IMBIRQ6:1;
VUINT32 IMBIRQ7:1;
VUINT32 IRQ2:1;
VUINT32 LVL2:1;
VUINT32 IMBIRQ8:1;
VUINT32 IMBIRQ9:1;
VUINT32 IMBIRQ10:1;
VUINT32 IMBIRQ11:1;
VUINT32 IRQ3:1;
VUINT32 LVL3:1;
VUINT32 IMBIRQ12:1;
VUINT32 IMBIRQ13:1;
VUINT32 IMBIRQ14:1;
VUINT32 IMBIRQ15:1;
VUINT32 IRQ4:1;
VUINT32 LVL4:1;
VUINT32 IMBIRQ16:1;
VUINT32 IMBIRQ17:1;
VUINT32 IMBIRQ18:1;
VUINT32 IMBIRQ19:1;
VUINT32 IRQ5:1;
VUINT32 LVL5:1;
} B;
} SISR2;
union {
VUINT32 R;
struct {
VUINT32 IMBIRQ20:1;
VUINT32 IMBIRQ21:1;
VUINT32 IMBIRQ22:1;
VUINT32 IMBIRQ23:1;
VUINT32 IRQ6:1;
VUINT32 LVL6:1;
VUINT32 IMBIRQ24:1;
VUINT32 IMBIRQ25:1;
VUINT32 IMBIRQ26:1;
VUINT32 IMBIRQ27:1;
VUINT32 IRQ7:1;
VUINT32 LVL7:1;
VUINT32 IMBIRQ28:1;
VUINT32 IMBIRQ29:1;
VUINT32 IMBIRQ30:1;
VUINT32 IMBIRQ31:1;
VUINT32:16;
} B;
} SISR3;
VUINT32 res2[42];
/*Memory Controller Registers */
union {
VUINT32 R;
struct {
VUINT32 BA:17;
VUINT32 AT:3;
VUINT32 PS:2;
VUINT32 SST:1;
VUINT32 WP:1;
VUINT32:1;
VUINT32 BL:1;
VUINT32 WEBS:1;
VUINT32 TBDIP:1;
VUINT32 LBDIP:1;
VUINT32 SETA:1;
VUINT32 BI:1;
VUINT32 V:1;
} B;
} BR0;
union {
VUINT32 R;
struct {
VUINT32 AM:17;
VUINT32 ATM:3;
VUINT32 CSNT:1;
VUINT32 ACS:2;
VUINT32 EHTR:1;
VUINT32 SCY:4;
VUINT32 BSCY:3;
VUINT32 TRLX:1;
} B;
} OR0;
union {
VUINT32 R;
struct {
VUINT32 BA:17;
VUINT32 AT:3;
VUINT32 PS:2;
VUINT32 SST:1;
VUINT32 WP:1;
VUINT32:1;
VUINT32 BL:1;
VUINT32 WEBS:1;
VUINT32 TBDIP:1;
VUINT32 LBDIP:1;
VUINT32 SETA:1;
VUINT32 BI:1;
VUINT32 V:1;
} B;
} BR1;
union {
VUINT32 R;
struct {
VUINT32 AM:17;
VUINT32 ATM:3;
VUINT32 CSNT:1;
VUINT32 ACS:2;
VUINT32 EHTR:1;
VUINT32 SCY:4;
VUINT32 BSCY:3;
VUINT32 TRLX:1;
} B;
} OR1;
union {
VUINT32 R;
struct {
VUINT32 BA:17;
VUINT32 AT:3;
VUINT32 PS:2;
VUINT32 SST:1;
VUINT32 WP:1;
VUINT32:1;
VUINT32 BL:1;
VUINT32 WEBS:1;
VUINT32 TBDIP:1;
VUINT32 LBDIP:1;
VUINT32 SETA:1;
VUINT32 BI:1;
VUINT32 V:1;
} B;
} BR2;
union {
VUINT32 R;
struct {
VUINT32 AM:17;
VUINT32 ATM:3;
VUINT32 CSNT:1;
VUINT32 ACS:2;
VUINT32 EHTR:1;
VUINT32 SCY:4;
VUINT32 BSCY:3;
VUINT32 TRLX:1;
} B;
} OR2;
union {
VUINT32 R;
struct {
VUINT32 BA:17;
VUINT32 AT:3;
VUINT32 PS:2;
VUINT32 SST:1;
VUINT32 WP:1;
VUINT32:1;
VUINT32 BL:1;
VUINT32 WEBS:1;
VUINT32 TBDIP:1;
VUINT32 LBDIP:1;
VUINT32 SETA:1;
VUINT32 BI:1;
VUINT32 V:1;
} B;
} BR3;
union {
VUINT32 R;
struct {
VUINT32 AM:17;
VUINT32 ATM:3;
VUINT32 CSNT:1;
VUINT32 ACS:2;
VUINT32 EHTR:1;
VUINT32 SCY:4;
VUINT32 BSCY:3;
VUINT32 TRLX:1;
} B;
} OR3;
VUINT32 res3[8];
union {
VUINT32 R;
struct {
VUINT32:1;
VUINT32 BA:6;
VUINT32:3;
VUINT32 AT:3;
VUINT32:15;
VUINT32 DMCS:3;
VUINT32 DME:1;
} B;
} DMBR;
union {
VUINT32 R;
struct {
VUINT32:1;
VUINT32 AM:6;
VUINT32:3;
VUINT32 ATM:3;
VUINT32:19;
} B;
} DMOR;
VUINT32 res4[12];
union {
VUINT16 R;
struct {
VUINT16:8;
VUINT16 WPER0:1;
VUINT16 WPER1:1;
VUINT16 WPER2:1;
VUINT16 WPER3:1;
VUINT16:4;
} B;
} MSTAT;
VUINT16 res4a;
VUINT32 res4b[33];
/*System integration Timers */
union {
VUINT16 R;
struct {
VUINT16 TBIRQ:8;
VUINT16 REFA:1;
VUINT16 REFB:1;
VUINT16:2;
VUINT16 REFAE:1;
VUINT16 REFBE:1;
VUINT16 TBF:1;
VUINT16 TBE:1;
} B;
} TBSCR;
VUINT16 res4c;
union {
VUINT32 R;
VUINT32 B;
} TBREF0;
union {
VUINT32 R;
VUINT32 B;
} TBREF1;
VUINT32 res5[5];
union {
VUINT16 R;
struct {
VUINT16 RTCIRQ:8;
VUINT16 SEC:1;
VUINT16 ALR:1;
VUINT16:1;
VUINT16 M:1;
VUINT16 SIE:1;
VUINT16 ALE:1;
VUINT16 RTF:1;
VUINT16 RTE:1;
} B;
} RTCSC;
VUINT16 res5a;
union {
VUINT32 R;
VUINT32 B;
} RTC;
union {
VUINT32 R;
VUINT32 B;
} RTSEC;
union {
VUINT32 R;
VUINT32 B;
} RTCAL;
VUINT32 res6[4];
union {
VUINT16 R;
struct {
VUINT16 PIRQ:8;
VUINT16 PS:1;
VUINT16:4;
VUINT16 PIE:1;
VUINT16 PITF:1;
VUINT16 PTE:1;
} B;
} PISCR;
VUINT16 res6a;
union {
VUINT32 R;
struct {
VUINT32 PITC:16;
VUINT32:16;
} B;
} PITC;
union {
VUINT32 R;
struct {
VUINT32 PIT:16;
VUINT32:16;
} B;
} PITR;
VUINT32 res7[13];
/*Clocks and Reset */
union {
VUINT32 R;
struct {
VUINT32 DBCT:1;
VUINT32 COM:2;
VUINT32 DCSLR:1;
VUINT32 MFPDL:1;
VUINT32 LPML:1;
VUINT32 TBS:1;
VUINT32 RTDIV:1;
VUINT32 STBUC:1;
VUINT32 CQDS:1;
VUINT32 PRQEN:1;
VUINT32 RTSEL:1;
VUINT32 BUCS:1;
VUINT32 EBDF:2;
VUINT32 LME:1;
VUINT32 EECLK:2;
VUINT32 ENGDIV:6;
VUINT32:1;
VUINT32 DFNL:3;
VUINT32:1;
VUINT32 DFNH:3;
} B;
} SCCR;
union {
VUINT32 R;
struct {
VUINT32 MF:12;
VUINT32:1;
VUINT32 LOCS:1;
VUINT32 LOCSS:1;
VUINT32 SPLS:1;
VUINT32 SPLSS:1;
VUINT32 TEXPS:1;
VUINT32 TEXP_INVP:1;
VUINT32 TMIST:1;
VUINT32:1;
VUINT32 CSRC:1;
VUINT32 LPM:2;
VUINT32 CSR:1;
VUINT32 LOLRE:1;
VUINT32:1;
VUINT32 DIVF:5;
} B;
} PLPRCR;
union {
VUINT16 R;
struct {
VUINT16 EHRS:1;
VUINT16 ESRS:1;
VUINT16 LLRS:1;
VUINT16 SWRS:1;
VUINT16 CSRS:1;
VUINT16 DBHRS:1;
VUINT16 DBSRS:1;
VUINT16 JTRS:1;
VUINT16 OCCS:1;
VUINT16 ILBC:1;
VUINT16 GPOR:1;
VUINT16 GHRST:1;
VUINT16 GSRST:1;
VUINT16:3;
} B;
} RSR;
VUINT16 res7a;
union {
VUINT16 R;
struct {
VUINT16 COLIRQ:8;
VUINT16 COLIS:1;
VUINT16 :1;
VUINT16 COLIE:1;
VUINT16:5;
} B;
} COLIR;
VUINT16 res7B;
union {
VUINT16 R;
struct {
VUINT16:1;
VUINT16 LVSRS:4;
VUINT16 VSRDE:1;
VUINT16 LVDECRAM:1;
VUINT16:9;
} B;
} VSRMCR;
VUINT16 res7c;
VUINT32 res8[27];
/*System Inegration Timer Keys */
union {
VUINT32 R;
VUINT32 B;
} TBSCRK;
union {
VUINT32 R;
VUINT32 B;
} TBREF0K;
union {
VUINT32 R;
VUINT32 B;
} TBREF1K;
union {
VUINT32 R;
VUINT32 B;
} TBK;
VUINT32 res9[4];
union {
VUINT32 R;
VUINT32 B;
} RTCSCK;
union {
VUINT32 R;
VUINT32 B;
} RTCK;
union {
VUINT32 R;
VUINT32 B;
} RTSECK;
union {
VUINT32 R;
VUINT32 B;
} RTCALK;
VUINT32 res10[4];
union {
VUINT32 R;
VUINT32 B;
} PISCRK;
union {
VUINT32 R;
VUINT32 B;
} PITCK;
VUINT32 res11[14];
/*Clocks and Reset Keys */
union {
VUINT32 R;
VUINT32 B;
} SCCRK;
union {
VUINT32 R;
VUINT32 B;
} PLPRCRK;
union {
VUINT32 R;
VUINT32 B;
} RSRK;
};
#endif
/****************************************************************************/
/* MODULE :UIMB */
/****************************************************************************/
struct UIMB_tag {
union {
VUINT32 R;
struct {
VUINT32 STOP:1;
VUINT32 IRQMUX:2;
VUINT32 HSPEED:1;
VUINT32:28;
} B;
} UMCR;
VUINT32 res0[3];
union {
VUINT32 R;
VUINT32 B;
} UTSTCREG;
VUINT32 res1[3];
union {
VUINT32 R;
struct {
VUINT32 LVL0:1;
VUINT32 LVL1:1;
VUINT32 LVL2:1;
VUINT32 LVL3:1;
VUINT32 LVL4:1;
VUINT32 LVL5:1;
VUINT32 LVL6:1;
VUINT32 LVL7:1;
VUINT32 LVL8:1;
VUINT32 LVL9:1;
VUINT32 LVL10:1;
VUINT32 LVL11:1;
VUINT32 LVL12:1;
VUINT32 LVL13:1;
VUINT32 LVL14:1;
VUINT32 LVL15:1;
VUINT32 LVL16:1;
VUINT32 LVL17:1;
VUINT32 LVL18:1;
VUINT32 LVL19:1;
VUINT32 LVL20:1;
VUINT32 LVL21:1;
VUINT32 LVL22:1;
VUINT32 LVL23:1;
VUINT32 LVL24:1;
VUINT32 LVL25:1;
VUINT32 LVL26:1;
VUINT32 LVL27:1;
VUINT32 LVL28:1;
VUINT32 LVL29:1;
VUINT32 LVL30:1;
VUINT32 LVL31:1;
} B;
} UIPEND;
};
#ifdef __MWERKS__
#pragma pack(pop)
#endif
#ifdef __cplusplus
}
#endif
#endif
/*********************************************************************
*
* Copyright:
* MOTOROLA, INC. All Rights Reserved.
* You are hereby granted a copyright license to use, modify, and
* distribute the SOFTWARE so long as this entire notice is
* retained without alteration in any modified and/or redistributed
* versions, and that such modified versions are clearly identified
* as such. No licenses are granted by implication, estoppel or
* otherwise under any patents or trademarks of Motorola, Inc. This
* software is provided on an "AS IS" basis and without warranty.
*
* To the maximum extent permitted by applicable law, MOTOROLA
* DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED, INCLUDING
* IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
* PURPOSE AND ANY WARRANTY AGAINST INFRINGEMENT WITH REGARD TO THE
* SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF) AND ANY
* ACCOMPANYING WRITTEN MATERIALS.
*
* To the maximum extent permitted by applicable law, IN NO EVENT
* SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER (INCLUDING
* WITHOUT LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS
* INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY
* LOSS) ARISING OF THE USE OR INABILITY TO USE THE SOFTWARE.
*
* Motorola assumes no responsibility for the maintenance and support
* of this software
********************************************************************/
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