📄 at91sam7sxxx.h
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/*
**********************************************************************
* Micrium, Inc.
* 949 Crestview Circle
* Weston, FL 33327-1848
*
* uC/FS
*
* (c) Copyright 2001 - 2006, Micrium, Inc.
* All rights reserved.
*
***********************************************************************
--------------------------------|
// |31-24|23-18|17----8|7---4|3----0|
// | KEY | --- | PAGEN | --- | FCMD | 256K flash part: 1024 pages of 256 bytes/page
// |__8__|__6__|___10__|__4__|__4___| 64K flash part: 512 pages of 128 bytes/page
// | | | | |
/**** bits of MC_FCR, end ***********************************************************/
/**** bits of SPI_CR, begin *********************************************************/
// SPI_CR, 0xFFFE_0000, SPI Control Register
// |---------------------------------------------------|
// |31-25|24------24|23--8|7-----7|6-2|1------1|0-----0|
// | --- | LASTXFER | --- | SWRST | - | SPIDIS | SPIEN |
// |__7__|____1_____|_16__|___1___|_5_|___1____|___1___|
// | | | | |
#define AT91C_SPI_NO_LASTXFER ((unsigned int) 0x0 << 24) // not used here
/**** bits of SPI_CR, end ***********************************************************/
/**** bits of SPI_MR, begin *********************************************************/
// SPI_MR, 0xFFFE_0004, SPI Mode Register
// |-------------------------------------------------------------------------|
// |31----24|23-20|19-16|15-8|7---7|6-5|4-------4|3----3|2------2|1--1|0----0|
// | DLYBCS | --- | PCS | -- | LLB | - | MODFDIS | FDIV | PCSDEC | PS | MSTR |
// |___8____|__4__|__4__|_8__|__1__|_2_|____1____|___1__|___1____|__1_|__1___|
// | | | | |
#define AT91C_SPI_NO_PCS ((unsigned int) 0x0 << 16) // PCS not used here (PS=1)
#define AT91C_SPI_NO_LLB ((unsigned int) 0x0 << 7) // normal operatioin (no loopback)
#define AT91C_SPI_NO_MODFDIS ((unsigned int) 0x1 << 4) // Mode Fault Detection disabled
#define AT91C_SPI_NO_FDIV ((unsigned int) 0x0 << 3) // FDIV=0
#define AT91C_SPI_NO_PCSDEC ((unsigned int) 0x0 << 2) // no chip select decoding
#define AT91C_SPI_SLAVE ((unsigned int) 0x0 << 0) // Slave Mode
/**** bits of SPI_MR, end ***********************************************************/
/**** bits of SPI_CSRx, begin *******************************************************/
// SPI_CSR0, 0xFFFE_0030, SPI Chip select Register 0
// SPI_CSR1, 0xFFFE_0034, SPI Chip select Register 1
// SPI_CSR2, 0xFFFE_0038, SPI Chip select Register 2
// SPI_CSR3, 0xFFFE_003C, SPI Chip select Register 3
// |---------------------------------------------------------|
// |31----24|24---16|15---8|7----4|3-----3|2-2|1-----1|0----0|
// | DLYBCT | DLYBS | SCBR | BITS | CSAAT | - | NCPHA | CPOL |
// |___8____|___8___|__8___|___4__|___1___|_1_|___1___|___1__|
// | | | | |
#define AT91C_SPI_NO_CSAAT ((unsigned int) 0x0 << 2) // chip select inactive after last transfer
#define AT91C_SPI_NO_NCPHA ((unsigned int) 0x0 << 1) // change leading, capture trailing
#define AT91C_SPI_NO_CPOL ((unsigned int) 0x0 << 0) // SPCK is inactive low
/**** bits of SPI_CSRx, end *********************************************************/
/**** bits of SPI_RPR, begin ********************************************************/
// SPI_RPR, 0xFFFE_0100, SPI PDC Receive Pointer Register
// |-------|
// |31----0|
// | RXPTR |
// |___32__|
// | | | | |
/**** bits of SPI_RPR, end **********************************************************/
/**** bits of SPI_RCR, begin ********************************************************/
// SPI_RCR, 0xFFFE_0104, SPI PDC Receive Counter Register
// |-------------|
// |31-16|15----0|
// | --- | RXCTR |
// |_16__|__16___|
// | | | | |
/**** bits of SPI_RCR, end **********************************************************/
/**** bits of SPI_TPR, begin ********************************************************/
// SPI_TPR, 0xFFFE_0108, SPI PDC Transmit Pointer Register
// |-------|
// |31----0|
// | TXPTR |
// |___32__|
// | | | | |
/**** bits of SPI_TPR, end **********************************************************/
/**** bits of SPI_TCR, begin ********************************************************/
// SPI_TCR, 0xFFFE_010C, SPI PDC Transmit Counter Register
// |-------------|
// |31-16|15----0|
// | --- | TXCTR |
// |_16__|__16___|
// | | | | |
/**** bits of SPI_TCR, end **********************************************************/
/**** bits of SPI_RNPR, begin *******************************************************/
// SPI_RNPR, 0xFFFE_0110, SPI PDC Receive Next Pointer Register
// |--------|
// |31-----0|
// | RXNPTR |
// |___32___|
// | | | | |
/**** bits of SPI_RNPR, end *********************************************************/
/**** bits of SPI_RNCR, begin *******************************************************/
// SPI_RNCR, 0xFFFE_0114, SPI PDC Receive Next Counter Register
// |--------------|
// |31-16|15-----0|
// | --- | RXNCTR |
// |_16__|___16___|
// | | | | |
/**** bits of SPI_RNCR, end *********************************************************/
/**** bits of SPI_TNPR, begin *******************************************************/
// SPI_TNPR, 0xFFFE_0118, SPI PDC Transmit Next Pointer Register
// |--------|
// |31-----0|
// | TXNPTR |
// |___32___|
// | | | | |
/**** bits of SPI_TNPR, end *********************************************************/
/**** bits of SPI_TNCR, begin *******************************************************/
// SPI_TNCR, 0xFFFE_011C, SPI PDC Transmit Next Counter Register
// |--------------|
// |31-16|15-----0|
// | --- | TXNCTR |
// |_16__|___16___|
// | | | | |
/**** bits of SPI_TNCR, end *********************************************************/
/**** bits of SPI_PTCR, begin *******************************************************/
// SPI_PTCR, 0xFFFE_0120, SPI PDC Transfer Control Register
// |-------------------------------------------|
// |31-10|9------9|8-----8|7-2|1------1|0-----0|
// | --- | TXTDIS | TXTEN | - | RXTDIS | RXTEN |
// |_22__|___1____|___1___|_6_|___1____|___1___|
// | | | | |
/**** bits of SPI_TNCR, end *********************************************************/
/**** bits of SPI_PTSR, begin *******************************************************/
// SPI_PTSR, 0xFFFE_0124, SPI PDC Transfer Status Register
// |------------------------|
// |31-9|8-----8|7-1|0-----0|
// | -- | TXTEN | - | RXTEN |
// |_23_|___1___|_7_|___1___|
// | | | | |
/**** bits of SPI_TNCR, end *********************************************************/
/**** bits of AIC_SMRx, begin *******************************************************/
// AIC_SMR0, 0xFFFF_F000, AIC Source Mode Register 0 (FIQ)
// AIC_SMR1, 0xFFFF_F004, AIC Source Mode Register 1 (System Interrupt = timer,RTC,PMC,MC)
// AIC_SMR2, 0xFFFF_F008, AIC Source Mode Register 2
// ...
// AIC_SMR31, 0xFFFF_F07C, AIC Source Mode Register 31
// |----------------------------|
// |31---7|6-------5|4-3|2-----0|
// | ---- | SRCTYPE | - | PRIOR |
// |__25__|____2____|_2_|___3___|
// | | | | |
#define AT91C_AIC_PRIOR_0 AT91C_AIC_PRIOR_LOWEST
#define AT91C_AIC_PRIOR_1 ((unsigned int) 0x1)
#define AT91C_AIC_PRIOR_2 ((unsigned int) 0x2)
#define AT91C_AIC_PRIOR_3 ((unsigned int) 0x3)
#define AT91C_AIC_PRIOR_4 ((unsigned int) 0x4)
#define AT91C_AIC_PRIOR_5 ((unsigned int) 0x5)
#define AT91C_AIC_PRIOR_6 ((unsigned int) 0x6)
#define AT91C_AIC_PRIOR_7 AT91C_AIC_PRIOR_HIGHEST
/**** bits of AIC_SMRx, end *********************************************************/
/**** bits of DBGU_CR, begin ********************************************************/
// DBGU_CR, 0xFFFE_F200, Debug Unit Control Register
// |----------------------------------------------------------------|
// |31--9|8------8|7-----7|6----6|5-----5|4----4|3-----3|2-----2|1-0|
// | --- | RSTSTA | TXDIS | TXEN | RXDIS | RXEN | RSTTX | RSTRX | - |
// |__23_|___1____|___1___|___1__|___1___|___1__|___1___|___1___|_2_|
// | | | | |
#define AT91C_US_RSTSTA ((unsigned int) 0x1 << 8) // (DBGU) Reset Status Bits
/**** bits of DBGU_CR, end **********************************************************/
/**** bits of RSTC_CR, begin ********************************************************/
// RSTC_CR, 0xFFFE_FD00, Reset Controller Control Register
// |------------------------------------------|
// |31-24|23-4|3------3|2------2|1-1|0-------0|
// | KEY | -- | EXTRST | PERRST | - | PROCRST |
// |__8__|_20_|___1____|___1____|_1_|____1____|
// | | | | |
#define RSTC_KEY 0xA5000000
/**** bits of RSTC_CR, end **********************************************************/
/**** bits of TC_CMR, begin *********************************************************/
// TC0_CMR, 0xFFFA_0004, TC Channel 0 Mode Register: Waveform Mode
// TC1_CMR, 0xFFFA_0044, TC Channel 1 Mode Register
// TC2_CMR, 0xFFFA_0084, TC Channel 2 Mode Register
// |-------------------------------------------------------------|
// |31----30|29---28|27--26|25--24|23----22|21---20|19--18|17--16|
// | BSWTRG | BEEVT | BCPC | BCPB | ASWTRG | AEEVT | ACPC | ACPA |
// |___2____|___2___|___2__|___2__|___2____|___2___|___2__|___2__|
// | | |
// |----------------------------------------------------------------------------------------|
// |15----15|14-----13|12----12|11--10|9-------8|7------7|6-------6|5-----4|3----3|2-------0|
// | WAVE=1 | WAVESEL | ENETRG | EEVT | EEVTEDG | CPCDIS | CPCSTOP | BURST | CLKI | TCCCLKS |
// |____1___|____2____|____1___|___2__|____2____|___1____|____1____|___2___|___1__|____3____|
// | | |
#define AT91C_TC_NO_ENETRG ((unsigned int) 0x0 << 12) // (TC) No External Event Trigger enable
#define AT91C_TC_NO_CPCDIS ((unsigned int) 0x0 << 7) // (TC) Counter Clock Not Disabled with RC Compare
#define AT91C_TC_NO_CPCSTOP ((unsigned int) 0x0 << 6) // (TC) Counter Clock Not Stopped with RC Compare
#define AT91C_TC_NO_CLKI ((unsigned int) 0x0 << 3) // (TC) No Clock Invert
#define AT91C_TC_CLKS_MCK_DIV_1024 AT91C_TC_CLKS_TIMER_DIV5_CLOCK
/**** bits of TC_CMR, end ***********************************************************/
#endif /* AT91SAM7SXXX_H */
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