dp83815.h

linux下的DP83815网卡驱动源码

#define DP_BMSR_100_HD_ABLE     (u16)0x2000 /* 100BASE-TX Half Duplex Capable */
#define DP_BMSR_100_FD_ABLE     (u16)0x4000 /* 100BASE-TX Full Duplex Capable */
#define DP_BMSR_100T4_ABLE      (u16)0x8000 /* 100BASE -T4 Capable */

/* PHY Identifier Register #1 */

#define DP_PHYIDR1_OUI_MSB      (u16)0xFFFF /* OUI Most significant Bits */

/* PHY Identifier Register #2 */

#define DP_PHYIDR2_MDL_REV      (u16)0x000F /* Model Revision number */
#define DP_PHYIDR2_VNDR_MDL     (u16)0x03F0 /* Vendor Model Number */
#define DP_PHYIDR2_OUI_LSB      (u16)0xFC00 /* OUI Last Significant Bits */

/*
 * Auto-Negotiation Advertisement Register
 *
 * Contains the advertised abilities of this device as they will be transmitted
 * to its link partner during Auto-Negotiation.
 */

#define DP_ANAR_SEL             (u16)0x001F /* Protocol Selection Bits */
#define DP_ANAR_10T             (u16)0x0020 /* 10BASE-T Support */
#define DP_ANAR_10_FD           (u16)0x0040 /* 10BASE-T Full Duplex Support */
#define DP_ANAR_TX              (u16)0x0080 /* 100BASE-TX Support */
#define DP_ANAR_TX_FD           (u16)0x0100 /* 100BASE-TX Full Duplex Support */
#define DP_ANAR_T4              (u16)0x0200 /* 100BASE-T4 Support */
#define DP_ANAR_PAUSE           (u16)0x0400 /* Pause */
#define DP_ANAR_RF              (u16)0x2000 /* Remote Fault */
#define DP_ANAR_NP              (u16)0x8000 /* Next Page Indication */

/*
 * Auto-Negotiation Link Partner Ability Register
 *
 * Contains the advertised abilities of the Link Partner as recieved during
 * Auto Negotiation. The content changes after the successful autonegotiation
 * if Next-Pages are supported.
 */

#define DP_ANLPAR_SEL           (u16)0x001F /* Protocol Selection Bits */
#define DP_ANLPAR_10T           (u16)0x0020 /* 10BASE-T Support */
#define DP_ANLPAR_10_FD         (u16)0x0040 /* 10BASE-T Full Duplex */
#define DP_ANLPAR_TX            (u16)0x0080 /* 100BASE-TX Support */
#define DP_ANLPAR_TX_FD         (u16)0x0100 /* 100BASE-TX Full Duplex */
#define DP_ANLPAR_T4            (u16)0x0200 /* 100BASE-T4 Support */
#define DP_ANLPAR_RF            (u16)0x2000 /* Remote Fault */
#define DP_ANLPAR_ACK           (u16)0x4000 /* Acknowledge */
#define DP_ANLPAR_NP            (u16)0x8000 /* Next Page Indication */

/*
 * Auto-Negotiation Expansion Register
 *
 * contains additional Local device and Link Partner status info
 */

#define DP_ANER_LP_AN_ABLE      (u16)0x0001 /* Link Partner Auto Neg Able */
#define DP_ANER_PAGE_RX         (u16)0x0002 /* Link Code Word Page Recvd */
#define DP_ANER_NP_ABLE         (u16)0x0004 /* Next Page Able */
#define DP_ANER_LP_NP_ABLE      (u16)0x0008 /* Link Partner NextPage Able */
#define DP_ANER_PDF             (u16)0x0010 /* Parallel Detection Fault */

/*
 * Auto-Negotiation Next page Transmit Register
 *
 * contains the next page Info sent by this device to its Link Partner 
 * during Auto-Negotiation
 */

#define DP_ANNPTR_CODE          (u16)0x07FF /* Code Field */
#define DP_ANNPTR_TOG_TX        (u16)0x0800 /* Toggle */
#define DP_ANNPTR_ACK2          (u16)0x1000 /* Acknowledge2 */
#define DP_ANNPTR_MP            (u16)0x2000 /* Message Page */
#define DP_ANNPTR_NP            (u16)0x8000 /* Next Page Indication */

/*
 * PHY Status Register
 *
 * provides a single location within the register set for quick access to
 * commonly accessed information
 */

#define DP_PHYSTS_LNK_VALID     (u16)0x0001 /* Valid Link */
#define DP_PHYSTS_SPEED_10      (u16)0x0002 /* 10 Mbps Mode */
#define DP_PHYSTS_FDX           (u16)0x0004 /* Full Duplex Mode */
#define DP_PHYSTS_LOOP          (u16)0x0008 /* Loopback Enabled */
#define DP_PHYSTS_ANEG_DONE     (u16)0x0010 /* Auto-Neg Complete */
#define DP_PHYSTS_JABBER        (u16)0x0020 /* Jabbler Detected */
#define DP_PHYSTS_REM_FAULT     (u16)0x0040 /* Remote Fault Detected */
#define DP_PHYSTS_MII_INTR      (u16)0x0080 /* MII Interrupt Pending */
#define DP_PHYSTS_LCWP_RX       (u16)0x0100 /* Link Code Word Page Rx'd */
#define DP_PHYSTS_DSCRMBL_LCK   (u16)0x0200 /* 100TX Descrambler Lock */
#define DP_PHYSTS_SIG_DET       (u16)0x0400 /* 100TX Uncond Signal Detect */
#define DP_PHYSTS_FCSL          (u16)0x0800 /* False Carrier Sense Latch */
#define DP_PHYSTS_POL_INV       (u16)0x1000 /* Polarity status */
#define DP_PHYSTS_RX_ERR_LATCH  (u16)0x2000 /* Received error latch */

/*
 * False carrier Sense Counter Register
 *
 * provides info required to implement the "FalseCarriers" attribute within
 * the MAJ managed object class of Clause 30 of the IEEE 802.3u specification.
 */

#define DP_FCSCR_FCSCNT         (u16)0x00FF /* False Carrier Event Counter */

/*
 * Receiver Error Counter Register
 *
 * provides info required to implement the "SymbolErrorDuringCarrier" attribute
 * within  the PHY managed object class of Clause 30 of the IEEE 802.3u
 * specification.  
 */

#define DP_RECR_RXERCNT         (u16)0x00FF /* RX_ER Counter*/

/* 100Mb/s PCS Configuration and Status Register */

#define DP_PCSR_NRZI_BYP        (u16)0x0004 /* NRZI Bypass Enable */
#define DP_PCSR_FRC_100_OK      (u16)0x0020 /* Force 100Mb/s Good Link */
#define DP_PCSR_SD_OPT          (u16)0x0100 /* Signal Detect Option */
#define DP_PCSR_SD_F_B          (u16)0x0200 /* Signal Detect Force */
#define DP_PCSR_TQ_EN           (u16)0x0400 /* 100Mbs True Quite Mode En */
#define DP_PCSR_FREE_CLK        (u16)0x0800 /* Receive Clock */
#define DP_PCSR_BYP_4B5B        (u16)0x1000 /* Bypass 4B/5B Encoding */

/* PHY Control Register */

#define DP_PHYCR_PHYADDR        (u16)0x001F /* PHY Address */
#define DP_PHYCR_LED_CFG        (u16)0x0060 /* LED Configuration */
#define DP_PHYCR_LED_CFG_10_HI  (u16)0x0000 /* Speed10 HIGH */
#define DP_PHYCR_LED_CFG_10     (u16)0x0020 /* Speed10 selected */
#define DP_PHYCR_LED_CFG_DPLXHI (u16)0x0040 /* DPLX active HIGH */
#define DP_PHYCR_LED_CFG_DPLX   (u16)0x0060 /* DPLX selected */
#define DP_PHYCR_PAUSE_PASS     (u16)0x0080 /* Pause Compare Pass */
#define DP_PHYCR_BP_STRETCH     (u16)0x0100 /* Bypass LED Stretch*/
#define DP_PHYCR_BIST_START     (u16)0x0200 /* BIST Start */
#define DP_PHYCR_BIST_PASS      (u16)0x0400 /* BIST Pass */
#define DP_PHYCR_PSR_15         (u16)0x0800 /* BIST Sequence Sel PSR15 (PSR9) */

/* 10Base-T Status/Control Register(10BTSCR) */

#define DP_10BTSCR_JABR_DIS     (u16)0x0001 /* Jabber Disable */ 
#define DP_10BTSCR_HB_DIS       (u16)0x0002 /* Heartbeat Disable */ 
#define DP_10BTSCR_LOW_SQL      (u16)0x0004 /* Reduced Sqyelch Enable */ 
#define DP_10BTSCR_AUTOPOL_DIS  (u16)0x0008 /* Auto Polarity Disable */
#define DP_10BTSCR_POL          (u16)0x0010 /* 10Mb Polarity Status */ 
#define DP_10BTSCR_FRC_POL_COR  (u16)0x0020 /* Force 10Mb Polarity Correction */
#define DP_10BTSCR_FRC_10       (u16)0x0040 /* Force 10Mb Good Link */ 
#define DP_10BTSCR_LP_DIS       (u16)0x0080 /* Normal Link Pulse Disable */
#define DP_10BTSCR_LB10_DIS     (u16)0x0100 /* 10Base-T Loopback Disable */


/*
 * Transmit and receive descriptors
 *
 * DP83815 uses the same descriptor layout for both transmit and receive
 * descriptors.
 */

#define DP_DESC_SIZE            0x0C /* 3 words */

/* Descriptor Layout */

#define DP_DESC_LNK             0x00 /* Link field offset */
#define DP_DESC_CMDSTS          0x04 /* Command & Status offset */
#define DP_DESC_BUFPTR          0x08 /* Buffer pointer offset */

/* DP_DESC_CMDSTS - Descriptor Command and Status Definitions */

#define DP_DESC_CMDSTS_SIZE         (u32)0x00000FFF /* Size of data in bytes */
#define DP_DESC_CMDSTS_TX_CCNT      (u32)0x000F0000 /* Collision Count */
#define DP_DESC_CMDSTS_TX_EC        (u32)0x00100000 /* Excessive Collisions */
#define DP_DESC_CMDSTS_TX_OWC       (u32)0x00200000 /* Out of window collns */
#define DP_DESC_CMDSTS_TX_ED        (u32)0x00400000 /* Excessive deferrals */
#define DP_DESC_CMDSTS_TX_TD        (u32)0x00800000 /* Transmit deferrals */
#define DP_DESC_CMDSTS_TX_CRS       (u32)0x01000000 /* Carrier sense lost */
#define DP_DESC_CMDSTS_TX_TFU       (u32)0x02000000 /* Tx FIFO underrun */
#define DP_DESC_CMDSTS_TX_TXA       (u32)0x04000000 /* Tx abort */
#define DP_DESC_CMDSTS_RX_COL       (u32)0x00010000 /* Collision */
#define DP_DESC_CMDSTS_RX_LBP       (u32)0x00020000 /* Loopback packet */
#define DP_DESC_CMDSTS_RX_FAE       (u32)0x00040000 /* Frame align error */
#define DP_DESC_CMDSTS_RX_CRCE      (u32)0x00080000 /* CRC error */
#define DP_DESC_CMDSTS_RX_ISE       (u32)0x00100000 /* Invalid symbol error */
#define DP_DESC_CMDSTS_RX_RUNT      (u32)0x00200000 /* Runt packet */
#define DP_DESC_CMDSTS_RX_LONG      (u32)0x00400000 /* Long packet */
#define DP_DESC_CMDSTS_RX_DEST      (u32)0x01800000 /* Destination Class */
#define DP_DESC_CMDSTS_RX_DEST_REJ  (u32)0x00000000 /*  Packet Rejected */
#define DP_DESC_CMDSTS_RX_DEST_UNI  (u32)0x00800000 /*  Unicast packet */
#define DP_DESC_CMDSTS_RX_DEST_MC   (u32)0x01000000 /*  Multicast packet */
#define DP_DESC_CMDSTS_RX_DEST_BC   (u32)0x01800000 /*  Broadcast packet */
#define DP_DESC_CMDSTS_RX_RXO       (u32)0x02000000 /* Receive overrun */
#define DP_DESC_CMDSTS_RX_RXA       (u32)0x04000000 /* Receive aborted */
#define DP_DESC_CMDSTS_OK           (u32)0x08000000 /* Packet OK */
#define DP_DESC_CMDSTS_TX_SUPCRC    (u32)0x10000000 /* Supress CRC */
#define DP_DESC_CMDSTS_RX_INCCRC    (u32)0x10000000 /* Include CRC */
#define DP_DESC_CMDSTS_INTR         (u32)0x20000000 /* Interrupt */
#define DP_DESC_CMDSTS_MORE         (u32)0x40000000 /* More descriptors */
#define DP_DESC_CMDSTS_OWN          (u32)0x80000000 /* Descr owner (consumer) */

#define DP_DESC_CMDSTS_TX_COLLISIONS_GET(cmdsts)	 			\
        (((cmdsts) & DP_DESC_CMDSTS_TX_CCNT) >> 16)

#define DP_DESC_CMDSTS_TX_ERRORS    (DP_DESC_CMDSTS_TX_CCNT |		        \
                                     DP_DESC_CMDSTS_TX_EC   |			\
                                     DP_DESC_CMDSTS_TX_OWC  |			\
                                     DP_DESC_CMDSTS_TX_ED   |			\
                                     DP_DESC_CMDSTS_TX_CRS  |			\
                                     DP_DESC_CMDSTS_TX_TFU  |			\
                                     DP_DESC_CMDSTS_TX_TXA)				

#define DP_DESC_CMDSTS_RX_ERRORS    (DP_DESC_CMDSTS_RX_RXA  |			\
                                     DP_DESC_CMDSTS_RX_RXO  |			\
                                     DP_DESC_CMDSTS_RX_LONG |			\
                                     DP_DESC_CMDSTS_RX_RUNT |			\
                                     DP_DESC_CMDSTS_RX_CRCE |			\
                                     DP_DESC_CMDSTS_RX_FAE)

#endif /* __DP83815_H__ */