dp83815.h

linux下的DP83815网卡驱动源码

#define DP_IMR_RXIDLE            (u32)0x00000010 /* Rx Idle */
#define DP_IMR_RXORN             (u32)0x00000020 /* Rx Overrun */
#define DP_IMR_TXOK              (u32)0x00000040 /* Tx Packet Ok */
#define DP_IMR_TXDESC            (u32)0x00000080 /* Tx Descriptor */
#define DP_IMR_TXERR             (u32)0x00000100 /* Tx Packet Error */
#define DP_IMR_TXIDLE            (u32)0x00000200 /* Tx Idle */
#define DP_IMR_TXURN             (u32)0x00000400 /* Tx Underrun */
#define DP_IMR_MIB               (u32)0x00000800 /* MIB Service */
#define DP_IMR_SWI               (u32)0x00001000 /* Software Interrupt */
#define DP_IMR_PME               (u32)0x00002000 /* Power Management Event */
#define DP_IMR_PHY               (u32)0x00004000 /* Phy Interrupt */
#define DP_IMR_HIERR             (u32)0x00008000 /* High Bits error set */
#define DP_IMR_RXSOVR            (u32)0x00010000 /* Rx Status FIFO Overrun */
#define DP_IMR_RTABT             (u32)0x00100000 /* Recieved Target Abort */
#define DP_IMR_RMABT             (u32)0x00200000 /* Recieved Master Abort */
#define DP_IMR_SSERR             (u32)0x00400000 /* Signaled System Error */
#define DP_IMR_DPERR             (u32)0x00800000 /* Detected Parity Error */
#define DP_IMR_RXRCMP            (u32)0x01000000 /* Receive Reset Complete */
#define DP_IMR_TXRCMP            (u32)0x02000000 /* Transmit Reset Complete */

/*
 * Interrupt Enable Register Bit Masks (DP_IER)
 *
 * Enable or disable DP chip interrupts
 */

#define DP_IER_IE               (u32)0x00000001 /* Interrupt Enable */
#define DP_IER_ID               (u32)0x00000000 /* Interrupt Disable */

/* Transmit descriptor Pointer Register Bit Mask (DP_TXDP) */

#define DP_TXDP_MSK             (u32)0xFFFFFFFE /* Transmit Descriptor Ptr */

/* Transmit Configuration Register Bit Masks (DP_TXCFG) */

#define DP_TXCFG_DRTH           (u32)0x0000003F /* Tx Drain Threshold */
#define DP_TXCFG_FLTH           (u32)0x00003F00 /* Tx Fill Threshold */
#define DP_TXCFG_MXDMA          (u32)0x00700000 /* Max DMA Burst Size */ 
#define DP_TXCFG_MXDMA_1        (u32)0x00100000 /* 1 32-bit word */
#define DP_TXCFG_MXDMA_2        (u32)0x00200000 /* 2 32-bit words */
#define DP_TXCFG_MXDMA_4        (u32)0x00300000 /* 4 32-bit words */
#define DP_TXCFG_MXDMA_8        (u32)0x00400000 /* 8 32-bit words */
#define DP_TXCFG_MXDMA_16       (u32)0x00500000 /* 16 32-bit words */
#define DP_TXCFG_MXDMA_32       (u32)0x00600000 /* 32 32-bit words */
#define DP_TXCFG_MXDMA_64       (u32)0x00700000 /* 64 32-bit words */
#define DP_TXCFG_MXDMA_128      (u32)0x00000000 /* 128 32-bit words */
#define DP_TXCFG_IFG            (u32)0x0C000000 /* Interframe gap Time */ 
#define DP_TXCFG_ATP            (u32)0x10000000 /* Automatic Transmit Pad */ 
#define DP_TXCFG_MLB            (u32)0x20000000 /* MAC Loopback */
#define DP_TXCFG_HBI            (u32)0x40000000 /* HeartBeat Ignore */
#define DP_TXCFG_CSI            (u32)0x80000000 /* Carrier Sense Ignore */

#define	DP_TXCFG_DRTH_SET(X)	((X) & DP_TXCFG_DRTH)
#define DP_TXCFG_FLTH_SET(X)	(((X) << 8) & DP_TXCFG_FLTH)

/* Recieve Descriptor Pointer Register Bit Mask (DP_RXDP) */

#define DP_RXDP_MSK             (u32)0xFFFFFFFC /* Receive Descriptor Ptr */

/* Recieve Configuration Register Bit Masks (DP_RXCFG) */

#define DP_RXCFG_DRTH           (u32)0x0000003E /* Rx Drain Threshold */
#define DP_RXCFG_MXDMA          (u32)0x00700000 /* Max DMA Burst size */
#define DP_RXCFG_MXDMA_1        (u32)0x00100000 /* 1 32-bit words */
#define DP_RXCFG_MXDMA_2        (u32)0x00200000 /* 2 32-bit words */
#define DP_RXCFG_MXDMA_4        (u32)0x00300000 /* 4 32-bit words */
#define DP_RXCFG_MXDMA_8        (u32)0x00400000 /* 8 32-bit words */
#define DP_RXCFG_MXDMA_16       (u32)0x00500000 /* 16 32-bit words */
#define DP_RXCFG_MXDMA_32       (u32)0x00600000 /* 32 32-bit words */
#define DP_RXCFG_MXDMA_64       (u32)0x00700000 /* 64 32-bit words */
#define DP_RXCFG_MXDMA_128      (u32)0x00000000 /* 128 32-bit words */
#define DP_RXCFG_ALP            (u32)0x08000000 /* Accept Long Packets */
#define DP_RXCFG_ATX            (u32)0x10000000 /* Accept transmit packets */
#define DP_RXCFG_ARP            (u32)0x40000000 /* Accept Runt Packets */
#define DP_RXCFG_AEP            (u32)0x80000000 /* Accept Errored Packets */

#define	DP_RXCFG_DRTH_SET(X)	((X) & DP_RXCFG_DRTH)

/*
 * Wake Command/status Register Bit Masks (DP_WCSR)
 *
 * It is used to configure/control and monitor DP83815 Wake Od LAN Logic
 * The Wake On LAN logic is used to monitor the incoming packet stream while
 * in a low-power state, and provide a wake event to the system if desired
 * packet type, contents, or Link change are detected. 
 */

#define DP_WCSR_WKPHY           (u32)0x00000001 /* Wake on Phy Interrupt */
#define DP_WCSR_WKUCP           (u32)0x00000002 /* Wake on unicast */
#define DP_WCSR_WKMCP           (u32)0x00000004 /* Wake on Multicast */
#define DP_WCSR_WKBCP           (u32)0x00000008 /* Wake on Broadcast */
#define DP_WCSR_WKARP           (u32)0x00000010 /* Wake on ARP */
#define DP_WCSR_WKPAT0          (u32)0x00000020 /* Wake on Pattern 0 match */
#define DP_WCSR_WKPAT1          (u32)0x00000040 /* Wake on Pattern 1 match */
#define DP_WCSR_WKPAT2          (u32)0x00000080 /* Wake on Pattern 2 match */
#define DP_WCSR_WKPAT3          (u32)0x00000100 /* Wake on Pattern 3 match */
#define DP_WCSR_WKMAG           (u32)0x00000200 /* Wake on Magic Packet */
#define DP_WCSR_MPSOE           (u32)0x00000400 /* Magic Packet SecureOn Enbl */
#define DP_WCSR_SOHACK          (u32)0x00200000 /* SecureOn Hack Attempt */
#define DP_WCSR_PHYINT          (u32)0x00400000 /* Phy Interrupt */
#define DP_WCSR_UCASTR          (u32)0x00800000 /* Unicast Recieved */
#define DP_WCSR_MCASTR          (u32)0x01000000 /* Multicast Recieved */
#define DP_WCSR_BCASTR          (u32)0x02000000 /* Broadcast Recieved */
#define DP_WCSR_ARPR            (u32)0x04000000 /* ARP Recieved */
#define DP_WCSR_PATM0           (u32)0x08000000 /* Pattern 0 match */
#define DP_WCSR_PATM1           (u32)0x10000000 /* Pattern 1 match */
#define DP_WCSR_PATM2           (u32)0x20000000 /* Pattern 2 match */
#define DP_WCSR_PATM3           (u32)0x40000000 /* Pattern 3 match */
#define DP_WCSR_MPR             (u32)0x80000000 /* Magic Packet Recieved */

/*
 * Pause Control/Status Register Bit Masks (DP_PCR)
 *
 * It is used to control and monitor the DP 83815 Pause Frame reception logic
 * The Pause frame reception logic is used to accept 802.3x Pause frames,
 * extract the pause length value, and initiate a TXMAV pause interval of the 
 * specified number of slot times.
 */

#define DP_PCR_PAUSE_CNT        (u32)0x0000FFFF /* Pause Counter value */
#define DP_PCR_MLD_EN           (u32)0x00010000 /* Manual Load Enable */
#define DP_PCR_PSNEG            (u32)0x00200000 /* Pause negotiated */
#define DP_PCR_PS_RCVD          (u32)0x00400000 /* Pause frame recieved */
#define DP_PCR_PS_ACT           (u32)0x00800000 /* Pause Active */
#define DP_PCR_PS_DA            (u32)0x20000000 /* Pause on DA */
#define DP_PCR_PS_MCAST         (u32)0x40000000 /* Pause on Multicast */
#define DP_PCR_PSEN             (u32)0x80000000 /* Pause Enable */

/* 
 * Recieve Filter/Match Control Register Bit Masks (DP_RFCR)
 *
 * It is used to control and configure the DP83815 Recieve Filter Control logic
 * The RFC logic is used to configure destination address filtering of incoming
 * packets.
 */

#define DP_RFCR_RFADDR          (u32)0x000003FF /* Rx Filter Extended RegAdd */ 
#define DP_RFCR_RFADDR_PMATCH1  (u32)0x00000000 /* Perfect Match octets 1-0 */
#define DP_RFCR_RFADDR_PMATCH2  (u32)0x00000002 /* Perfect Match octets 3-2 */
#define DP_RFCR_RFADDR_PMATCH3  (u32)0x00000004 /* Perfect Match octets 5-4 */ 
#define DP_RFCR_RFADDR_PCOUNT1  (u32)0x00000006 /* Pattern Count 1-0 */
#define DP_RFCR_RFADDR_PCOUNT2  (u32)0x00000008 /* Pattern Count 3-2 */
#define DP_RFCR_RFADDR_SOPAS1   (u32)0x0000000A /* SecureOn Password 1-0 */
#define DP_RFCR_RFADDR_SOPAS2   (u32)0x0000000C /* SecureOn Password 3-2 */
#define DP_RFCR_RFADDR_SOPAS3   (u32)0x0000000E /* SecureOn Password 5-4 */
#define DP_RFCR_RFADDR_FMEM_LO  (u32)0x00000200 /* Rx filter memory start */
#define DP_RFCR_RFADDR_FMEM_HI  (u32)0x000003FE /* Rx filter memory end */
#define DP_RFCR_ULM             (u32)0x00080000 /* U/L bit Mask */
#define DP_RFCR_UHEN            (u32)0x00100000 /* Unicast Hash Enable */
#define DP_RFCR_MHEN            (u32)0x00200000 /* Multicast Hash Enable */
#define DP_RFCR_AARP            (u32)0x00400000 /* Accept ARP Packets */
#define DP_RFCR_APAT            (u32)0x07800000 /* Accept On Pattern Match */
#define DP_RFCR_APM             (u32)0x08000000 /* Accept on Perfect match */
#define DP_RFCR_AAU             (u32)0x10000000 /* Accept All Unicast */
#define DP_RFCR_AAM             (u32)0x20000000 /* Accept All Multicast */
#define DP_RFCR_AAB             (u32)0x40000000 /* Accept All Broadcast */
#define DP_RFCR_RFEN            (u32)0x80000000 /* Rx Filter Enable */

/* 
 * Recieve Filter/Match Data Register Bit Masks (DP_RFDR)
 *
 * This register is used to read and write internal recieve filter registers,
 * the pattern buffer memory and the hash table memory.
 */

#define DP_RFDR_RFDATA          (u32)0x0000FFFF /* Recieve Filter data */
#define DP_RFDR_BMASK           (u32)0x00030000 /* Byte Mask */

/* Boot ROM Address Register Bit Masks (DP_BRAR) */

#define DP_BRAR_ADDR            (u32)0x0000FFFF /* Boot ROM Address */
#define DP_BRAR_AUTOINC         (u32)0x80000000 /* Auto-Increment */

/* Boot ROM Data Register Bit Masks (DP_BRDR) */

#define DP_BRDR_DATA            (u32)0xFFFFFFFF /* Boot ROM Data */

/* Silicon Revision Register Bit Masks (DP_SRR) */

#define DP_SRR_MIN              (u32)0x000000FF /* Minor Revision Level */
#define DP_SRR_MAJ              (u32)0x0000FF00 /* Major Revision Level */
#define	DP_SRR_MAJ_SHF			8               /* Shift bits */

/*
 * Management Information Base Control Register Bit Masks (DP_MIBC)
 *
 * It is used to control access to the statistics block and the warning bits
 * and to control the collection of management info statistics.
 */

#define DP_MIBC_WRN             (u32)0x00000001 /* Warning Tst Indicator (RO) */
#define DP_MIBC_FRZ             (u32)0x00000002 /* Freeze All Counters */
#define DP_MIBC_ACLR            (u32)0x00000004 /* Clear all Counters */
#define DP_MIBC_MIBS            (u32)0x00000008 /* MIB Counter Strobe (TEST) */

/* BMCR - (Internal Phy) Basic Mode Control Register */

#define DP_BMCR_COL_TST         (u16)0x0080 /* Collision Test */
#define DP_BMCR_HDX             (u16)0x0000 /* Half duplex mode */
#define DP_BMCR_FDX             (u16)0x0100 /* Full duplex mode */
#define DP_BMCR_ANEG_RES        (u16)0x0200 /* Restart Auto negotiation */
#define DP_BMCR_ISOLATE         (u16)0x0400 /* Isolate */
#define DP_BMCR_PWRDWN          (u16)0x0800 /* Power Down */
#define DP_BMCR_ANEG_EN         (u16)0x3100 /* Auto Negotiation Enable */
#define DP_BMCR_SPD_100         (u16)0x2000 /* Speed Select 100Mbps */
#define DP_BMCR_SPD_10          (u16)0x0000 /* Speed Select 100Mbps */
#define DP_BMCR_LOOP            (u16)0x4000 /* Loopback */
#define DP_BMCR_RESET           (u16)0x8000 /* Reset */

/* BMSR - (Internal Phy) Basic Mode Status Register */

#define DP_BMSR_XREG_ABLE       (u16)0x0001 /* Extended Register Capability */
#define DP_BMSR_JABR_DET        (u16)0x0002 /* Jabber Detected */
#define DP_BMSR_LNK_VALID       (u16)0x0004 /* Valid Link Status */
#define DP_BMSR_AN_ABLE         (u16)0x0008 /* Auto-Neg Ability */
#define DP_BMSR_REM_FLT         (u16)0x0010 /* Remote Fault Detected */
#define DP_BMSR_AN_DONE         (u16)0x0020 /* Auto Nego Complete */
#define DP_BMSR_PRS_ABLE        (u16)0x0040 /* Preamble Supr Capable */
#define DP_BMSR_10_HD_ABLE      (u16)0x0800 /* 10BASE-T Half Duplex Capable */
#define DP_BMSR_10_FD_ABLE      (u16)0x1000 /* 10BASE-T Full Duplex Capable */