dp83815.h

linux下的DP83815网卡驱动源码

/* dp83815.h -National DP83815 Ethernet Controller Interface */
/* This is the Rev 3 of the driver and the changes for the Rev C of DP83815 
 * have been included */ 

#ifndef __DP83815_H__
#define __DP83815_H__

#ifdef __KERNEL__
#include <linux/types.h>
#endif

#define DP_DEV_NAME        "National DP83815 Fast Ethernet PCI Adapter"
#define DP_DRV_NAME        "dp83815"

/* PCI Confiugration Registers */

#undef  PCI_VENDOR_ID_NS_83815
#define PCI_VENDOR_ID_NS_83815  0x0020 /* DP83815 */

#define	DP83815_PCI_IO_SIZE		256

/*
 * Operational Registers:
 * These registers mapped either into PCI memory space or I/O space.
 */

/* MAC/BIU Registers */

#define DP_CR               0x00 /* Command Register */
#define DP_CFG              0x04 /* Configuration Register */
#define DP_MEAR             0x08 /* EEPROM Access Register */
#define DP_PTSCR            0x0C /* PCI Test Control Register */
#define DP_ISR              0x10 /* Intr Status Register */
#define DP_IMR              0x14 /* Intr Mask Register */
#define DP_IER              0x18 /* Intr Enable Register */
#define DP_TXDP             0x20 /* Tx Descriptor Pointer Register */
#define DP_TXCFG            0x24 /* Tx Configuration Register */
#define DP_RXDP             0x30 /* Rx Descriptor Pointer Register */
#define DP_RXCFG            0x34 /* Rx Configuration Register */
#define DP_CCSR             0x3C /* CLKRUN control/Status Register */
#define DP_WCSR             0x40 /* Wake on LAN Control/Status Register */
#define DP_PCR              0x44 /* Pause Control/Status Register */
#define DP_RFCR             0x48 /* Rx Filter/Match Control Register */
#define DP_RFDR             0x4C /* Rx Filter/Match Data Register */
#define DP_BRAR             0x50 /* Boot ROM Address */
#define DP_BRDR             0x54 /* Boot ROM Data */
#define DP_SRR              0x58 /* Silicon Revision Register (RO) */
#define DP_MIBC             0x5C /* MIB Control Registor */
#define DP_MIB              0x60 /* MIB Data Register Base (RO) */

/* MIB Registers */

#define DP_MIB_RX_PKT_ERR   0x60 /* Pkts recvd with errors */
#define DP_MIB_RX_FCS_ERR   0x64 /* Pkts recvd with frame check seq errs */
#define DP_MIB_RX_MISS_PKT  0x68 /* Pkts missed due to FIFO  overruns*/
#define DP_MIB_RX_FA_ERR    0x6C /* Pkts recvd with frame alignment errs */
#define DP_MIB_RX_SYM_ERR   0x70 /* Pkts recvd with symbol errs */
#define DP_MIB_RX_LONG_FRM  0x74 /* Pkts > 1518 bytes */
#define DP_MIB_TXSQE_ERR    0x78 /* Loss of coll. heartbeat on Tx */

/* Internal Phy Registers */

#define DP_BMCR             0x80 /* Basic Mode Control Register */
#define DP_BMSR             0x84 /* Basic Mode Status Register (RO) */
#define DP_PHYIDR1          0x88 /* PHY Identifier Register #1 (RO) */
#define DP_PHYIDR2          0x8C /* PHY Identifier Register #2 (RO) */
#define DP_ANAR             0x90 /* Auto-Nego Advertisment Reg */
#define DP_ANLPAR           0x94 /* Auto-Nego Link Partner Ability Reg */
#define DP_ANER             0x98 /* Auto-Negotiation Expansion Reg */
#define DP_ANNPTR           0x9C /* Auto-Negotiation Next Page TX */
#define DP_PHYSTS           0xC0 /* PHY Status Register (RO) */
#define DP_PHYMICR	0xC4
#define DP_PHYMISR	    0xC8
#define DP_FCSCR            0xD0 /* False Carrier Sense Counter Reg */
#define DP_RECR             0xD4 /* Recv Error Counter Register */  
#define DP_PHYCR            0xE4 /* PHY Control Register */  
#define DP_10BTSCR          0xE8 /* 10Base-TStatus/Control Reg */ 

#define DP_MICR             0xC4 /* MII Interrupt controller */

#define DP_MICR_PHY_INT     0x4002
/* New Phy registers and their bit mask values for Rev 3 */    

#define DP_PHY_PAGE        0xCC /* */
#define	DP_PHY_DSPTST	   0xEC
#define DP_PHY_EXTCFG      0xF0 /*2000*/     
#define DP_PHY_DSPCFG      0xF4 /* */
#define DP_PHY_SDCFG       0xF8 /* */
#define DP_PHY_TDATA       0xFC /* */

#define DP_PHY_PAGE_VAL        (u16)0x0001 /* */
#define DP_PHY_DSPCFG_VAL      (u16)0x5040 /* Load/Kill C2 */
#define DP_PHY_SDCFG_VAL       (u16)0x008C /* Raise SD off, from 4 to C */
#define DP_PHY_TDATA_VAL       (u16)0x0000 /* Set value for C2 */
#define DP_PHYCR_PMDCSR_VAL    (u16)0x189C /* DC Speed = 01 */

/*
 * Command Register Bit Masks (DP_CR)
 *
 * This register is used for issuing commands to DP83815. A global software
 * reset along with individual reset and enable/disable switches for
 * transmitter and receiver are provided here.
 */

#define DP_CR_TXE           0x00000001 /* Transmit Enable */
#define DP_CR_TXD           0x00000002 /* Transmit Disable */
#define DP_CR_RXE           0x00000004 /* Receiver Enable */
#define DP_CR_RXD           0x00000008 /* Receiver Disable */
#define DP_CR_TXR           0x00000010 /* Transmit Reset */
#define DP_CR_RXR           0x00000020 /* Receiver Reset */
#define DP_CR_SWI           0x00000080 /* Software Interrupt */
#define DP_CR_RST           0x00000100 /* Reset */

/*
 * Configuration and Media Status Register Bit Masks (DP_CFG)
 *
 * This register allows configuration of a various device and phy options,
 * and provide phy status information.
 */

#define DP_CFG_BEM              (u32)0x00000001 /* Big Endian Mode (BM xfers) */
#define DP_CFG_BROM_DIS         (u32)0x00000004 /* Disable Boot ROM interface */
#define DP_CFG_PESEL            (u32)0x00000008 /* Parity Err Det (BM xfer) */
#define DP_CFG_EXD              (u32)0x00000010 /* Excessv Deferl Tmr disbl */ 
#define DP_CFG_POW              (u32)0x00000020 /* Prog Out of Window Timer */
#define DP_CFG_SB               (u32)0x00000040 /* Single Back-off */
#define DP_CFG_REQALG           (u32)0x00000080 /* PCI Bus Request Algorithm */
#define DP_CFG_EUPHCOMP         (u32)0x00000100 /* DP83810 Descriptor Compat */ 
#define DP_CFG_PHY_DIS          (u32)0x00000200 /* Disable internal Phy */
#define DP_CFG_PHY_RST          (u32)0x00000400 /* Reset internal Phy */
#define DP_CFG_ANEG_SEL         (u32)0x0000E000 /* Auto-nego Sel - Mask */
#define DP_CFG_ANEG_SEL_10_HD   (u32)0x00000000 /*  Force 10Mb Half duplex */
#define DP_CFG_ANEG_SEL_100_HD  (u32)0x00004000 /*  Force 100Mb Half duplex */
#define DP_CFG_ANEG_SEL_10_FD   (u32)0x00008000 /*  Force 10Mb Full duplex */
#define DP_CFG_ANEG_SEL_100_FD  (u32)0x0000C000 /*  Force 100Mb Full duplex */
#define DP_CFG_ANEG_SEL_10_XD   (u32)0x00002000 /*  Nego 10Mb Half/Full dplx */
#define DP_CFG_ANEG_SEL_ALL_HD  (u32)0x00006000 /*  Nego 10/100 Half duplex */
#define DP_CFG_ANEG_SEL_100_XD  (u32)0x0000A000 /*  Nego 100 Half/Full duplex */
#define DP_CFG_ANEG_SEL_ALL_XD  (u32)0x0000E000 /*  Nego 10/100 Half/Full dplx*/
#define DP_CFG_PAUSE_ADV        (u32)0x00010000 /* Strap for pause capable */
#define DP_CFG_PINT_ACEN        (u32)0x00020000 /* Phy Intr Auto Clr Enable */ 
#define DP_CFG_PHY_CFG          (u32)0x00FC0000 /* Phy Configuration */
#define DP_CFG_ANEG_DN          (u32)0x08000000 /* Auto-negotiation Done */
#define DP_CFG_POL              (u32)0x10000000 /* 10Mb Polarity Indication */
#define DP_CFG_FDUP             (u32)0x20000000 /* Full Duplex */
#define DP_CFG_SPEED100         (u32)0x40000000 /* Speed 100Mb */
#define DP_CFG_LNKSTS           (u32)0x80000000 /* Link status */

/*
 * EEPROM Access Register Bit Masks (DP_MEAR)
 *
 * Provides an interface for software access to the NMC9306 style EEPROM.  The
 * default values given assume that the EEDO line has a pullup resistor to
 * VDD.
 */

#define DP_MEAR_EEDI            (u32)0x00000001 /* EEPROM data in */
#define DP_MEAR_EEDO            (u32)0x00000002 /* EEPROM data out */
#define DP_MEAR_EECLK           (u32)0x00000004 /* EEPROM Serial Clock */
#define DP_MEAR_EESEL           (u32)0x00000008 /* EEPROM Chip Select */

/* PCI Test Control Register Bit Masks (DP_PTSCR) */

#define DP_PTSCR_EEBIST_FAIL    (u32)0x00000001 /* EE BIST Fail Indication */
#define DP_PTSCR_EEBIST_EN      (u32)0x00000002 /* Enable  EEPROM BIST */
#define DP_PTSCR_EELOAD_EN      (u32)0x00000004 /* Enable EEPROM Load */
#define DP_PTSCR_RBIST_RXFFAIL  (u32)0x00000008 /* RX Filter RAM BIST Fail */
#define DP_PTSCR_RBIST_TXFAIL   (u32)0x00000010 /* TX FiFO Fail */
#define DP_PTSCR_RBIST_RXFAIL   (u32)0x00000020 /* RX FIFO BIST Fail */
#define DP_PTSCR_RBIST_ACT      (u32)0x00000040 /* SRAM BIST Active*/
#define DP_PTSCR_RBIST_EN       (u32)0x00000080 /* SRAM BIST Enable */
#define DP_PTSCR_RBIST_MODE     (u32)0x00000100 /* SRAM BIST Mode */
#define DP_PTSCR_RBIST_CLKD     (u32)0x00000200 /* SRAM BIST Clock */
#define DP_PTSCR_RBIST_RST      (u32)0x00000400 /* SRAM BIST Reset */
#define DP_PTSCR_RESVD          (u32)0x00001000 /* Reserved -- Must be 1 */

/*
 * Interrupt Status Register Bit Masks (DP_ISR)
 *
 * Indicates the source of an interrupt when the INTA pin goes active.
 * Enabling the corresponding bit in the IMR allows bits in this reg to produce
 * an interrupt. ISR reflects all pending iterrupts regardless of the status
 * of the corresponding mask bit in the IMR.
 */

#define DP_ISR_RXOK             (u32)0x00000001 /* Rx OK */
#define DP_ISR_RXDESC           (u32)0x00000002 /* Rx Descriptor */
#define DP_ISR_RXERR            (u32)0x00000004 /* Rx packet Error */
#define DP_ISR_RXEARLY          (u32)0x00000008 /* Rx Early Threshold */
#define DP_ISR_RXIDLE           (u32)0x00000010 /* Rx Idle */
#define DP_ISR_RXORN            (u32)0x00000020 /* Rx Overrun */
#define DP_ISR_TXOK             (u32)0x00000040 /* Tx Packet OK */
#define DP_ISR_TXDESC           (u32)0x00000080 /* Tx Descriptor */
#define DP_ISR_TXERR            (u32)0x00000100 /* Tx Packet Error */
#define DP_ISR_TXIDLE           (u32)0x00000200 /* Tx Idle */
#define DP_ISR_TXURN            (u32)0x00000400 /* Tx Underrun */
#define DP_ISR_MIB              (u32)0x00000800 /* MIB Service */
#define DP_ISR_SWI              (u32)0x00001000 /* Software Interrupt */
#define DP_ISR_PME              (u32)0x00002000 /* Power Management Event */
#define DP_ISR_PHY              (u32)0x00004000 /* Phy Interrupt */
#define DP_ISR_HIBERR           (u32)0x00008000 /* High Bits error set */
#define DP_ISR_RXSOVR           (u32)0x00010000 /* Rx Status FIFO Overrun */
#define DP_ISR_RTABT            (u32)0x00100000 /* Recieved Target Abort */
#define DP_ISR_RMABT            (u32)0x00200000 /* Recieved Master Abort */
#define DP_ISR_SSERR            (u32)0x00400000 /* Signaled System Error */
#define DP_ISR_DPERR            (u32)0x00800000 /* Detected Parity Error */
#define DP_ISR_RXRCMP           (u32)0x01000000 /* Receive Reset Complete */
#define DP_ISR_TXRCMP           (u32)0x02000000 /* Transmit Reset Complete */

/*
 * Interrupt Mask Register Bit Masks (DP_IMR)
 *
 * Interrupts are enabled by setting the appropriate bit-mask.
 */

#define DP_IMR_RXOK              (u32)0x00000001 /* Rx ok */
#define DP_IMR_RXDESC            (u32)0x00000002 /* Rx Descriptor */
#define DP_IMR_RXERR             (u32)0x00000004 /* Rx packet Error */
#define DP_IMR_RXEARLY           (u32)0x00000008 /* Rx Early Threshold */