slic.h

linux下的SPI总线驱动程序

#define	BAT_V_LO_SENSE	83
#define	IQ1				84
#define	IQ2				85
#define	IQ3				86
#define	IQ4				87
#define	IQ5				88
#define	IQ6				89
#define	RESERVED90		90
#define	RESERVED91		91
#define	DCDC_PWM_OFF    92
#define	DCDC            93
#define	DCDC_PW_OFF     94
#define	RESERVED95      95
#define	CALIBR1         96
#define CALIBRATE_LINE  0x78
#define NORMAL_CALIBRATION_COMPLETE 0x20
#define	CALIBR2         97
#define	RING_GAIN_CAL   98
#define	TIP_GAIN_CAL    99
#define	DIFF_I_CAL      100
#define	COMMON_I_CAL    101
#define	I_LIMIT_GAIN_CAL 102
#define	ADC_OFFSET_CAL  103
#define	DAC_ADC_OFFSET  104
#define	DAC_OFFSET_CAL  105
#define	COMMON_BAL_CAL  106
#define	DC_PEAK_CAL     107
/*
@ register definition (indirect)
*/
#define	DTMF_ROW_0_PEAK	0
#define	DTMF_ROW_1_PEAK	1
#define	DTMF_ROW2_PEAK	2
#define	DTMF_ROW3_PEAK	3
#define	DTMF_COL1_PEAK	4
#define	DTMF_FWD_TWIST	5
#define	DTMF_RVS_TWIST	6
#define	DTMF_ROW_RATIO_THRESH	7
#define	DTMF_COL_RATIO_THRESH	8
#define	DTMF_ROW_2ND_HARM		9
#define	DTMF_COL_2ND_HARM		10
#define	DTMF_PWR_MIN_THRESH		11
#define	DTMF_HOT_LIM_THRESH		12
#define	OSC1_COEF		13
#define	OSC1X			14
#define	OSC1Y			15
#define	OSC2_COEF		16
#define	OSC2X			17
#define	OSC2Y			18
#define	RING_V_OFF		19
#define	RING_OSC_COEF	20
#define	RING_X			21
#define	RING_Y			22
#define	PULSE_ENVEL		23
#define	PULSE_X			24
#define	PULSE_Y			25
#define	RECV_DIGITAL_GAIN	26
#define	XMIT_DIGITAL_GAIN	27
#define	LOOP_CLOSE_THRESH	28
#define	RING_TRIP_THRESH	29
#define	COMMON_MIN_THRESH	30
#define	COMMON_MAX_THRESH	31
#define	PWR_ALARM_Q1Q2		32
#define	PWR_ALARM_Q3Q4		33
#define	PWR_ALARM_Q5Q6		34
#define	LOOP_CLOSURE_FILTER	35
#define	RING_TRIP_FILTER	36
#define	THERM_LP_POLE_Q1Q2	37
#define	THERM_LP_POLE_Q3Q4	38
#define	THERM_LP_POLE_Q5Q6	39
#define	CM_BIAS_RINGING		40
#define	DCDC_MIN_V			41
#define	DCDC_XTRA			42
#define ALL_CHIPS 			0x09
#define NO_CHIPS 			0
#define	REVC		108	/*		0	ilim_max	fsk_revc	dc_err_en	zs_ext	batsel_pd	lcr_sense	en_subtr	hyst_en	*/
#define	FSK_X_0		99	/*	x	sign				fsk_x_0[15:0]												*/
#define	FSK_COEFF_0	100	/*	x	sign				fsk_coeff_0[15:0]												*/
#define	FSK_X_1		101	/*	x	sign				fsk_x_1[15:0]												*/
#define	FSK_COEFF_1	102	/*	x	sign				fsk_coeff_1[15:0]												*/
#define	FSK_X_01	103	/*	x	sign				fsk_x_01[15:0]												*/
#define	FSK_X_10	104	/*	x	sign				fsk_x_10[15:0]												*/

/*--------------------------------------------------------
 *    Interrupt bits: direct 18
 *--------------------------------------------------------*/
#define O1AP (1<<0) /*OSC1 interrupt active timer*/
#define O1IP (1<<1) /*OSC1 interrupt inactive timer*/
#define O2AP (1<<2) /*OSC2 interrupt active timer*/
#define O2IP (1<<3) /*OSC2 interrupt inactive timer*/
#define RGAP (1<<4) /*Ring active timer interrupt*/
#define RGIP (1<<5) /*Ring inactive timer interrupt*/
#define PMAP (1<<6) /*Pulse meter active timer interrupt*/
#define PMIP (1<<7) /*Pusle meter inactive timer interrupt*/
/*--------------------------------------------------------
 *    Interrupt bits: direct 19
 *--------------------------------------------------------*/
#define RTIP (1<<0) /*Ring trip interrupt pending*/
#define LCIP (1<<1) /*Loop closure transition interrupt pending*/
#define Q1AP (1<<2) /*Q1 power alarm*/
#define Q2AP (1<<3) /*Q2 power alarm*/
#define Q3AP (1<<4) /*Q3 power alarm*/
#define Q4AP (1<<5) /*Q4 power alarm*/
#define Q5AP (1<<6) /*Q5 power alarm*/
#define Q6AP (1<<7) /*Q6 power alarm*/
/*--------------------------------------------------------
 *    Interrupt bits: direct 20
 *--------------------------------------------------------*/
#define DTMFP (1<<0) /*DTME tone detected*/
#define INDP  (1<<1) /*Indirect reg access serviced*/
#define CMCP  (1<<2) /*Common mode calibration error*/
/*--------------------------------------------------------
 *    Tone 
 *--------------------------------------------------------*/
#define	DIALTONE_IR13	0x7b30
#define	DIALTONE_IR14	0x0063	
#define	DIALTONE_IR16	0x7870	
#define	DIALTONE_IR17	0x007d	
#define	DIALTONE_DR32	6	
#define	DIALTONE_DR33	6	
#define	DIALTONE_DR36	0	
#define	DIALTONE_DR37	0	
#define	DIALTONE_DR38	0	
#define	DIALTONE_DR39	0	
#define	DIALTONE_DR40	0	
#define	DIALTONE_DR41	0	
#define	DIALTONE_DR42	0	
#define	DIALTONE_DR43	0	

#define	REORDERTONE_IR13	0x7700
#define	REORDERTONE_IR14	0x0089	
#define	REORDERTONE_IR16	0x7120	
#define	REORDERTONE_IR17	0x00B2	
#define	REORDERTONE_DR32	0x1E	
#define	REORDERTONE_DR33	0x1E	
#define	REORDERTONE_DR36	0x60	
#define	REORDERTONE_DR37	0x09	
#define	REORDERTONE_DR38	0x40	
#define	REORDERTONE_DR39	0x06	
#define	REORDERTONE_DR40	0x60	
#define	REORDERTONE_DR41	0x09	
#define	REORDERTONE_DR42	0x40	
#define	REORDERTONE_DR43	0x06	

#define	BUSYTONE_IR13	0x7700
#define	BUSYTONE_IR14	0x0089	
#define	BUSYTONE_IR16	0x7120	
#define	BUSYTONE_IR17	0x00B2	
#define	BUSYTONE_DR32	0x1E	
#define	BUSYTONE_DR33	0x1E	
#define	BUSYTONE_DR36	0xa0	
#define	BUSYTONE_DR37	0x0f	
#define	BUSYTONE_DR38	0xa0	
#define	BUSYTONE_DR39	0x0f	
#define	BUSYTONE_DR40	0xa0	
#define	BUSYTONE_DR41	0x0f	
#define	BUSYTONE_DR42	0xa0	
#define	BUSYTONE_DR43	0x0f	

#define	RINGBACKTONE_IR13	0x7870	
#define	RINGBACKTONE_IR14	0x007D	
#define	RINGBACKTONE_IR16	0x7700	
#define	RINGBACKTONE_IR17	0x0089	
#define	RINGBACKTONE_DR32	0x1E	
#define	RINGBACKTONE_DR33	0x1E	
#define	RINGBACKTONE_DR36	0x80	
#define	RINGBACKTONE_DR37	0x3E	
#define	RINGBACKTONE_DR38	0x0	
#define	RINGBACKTONE_DR39	0x7d	
#define	RINGBACKTONE_DR40	0x80	
#define	RINGBACKTONE_DR41	0x3E	
#define	RINGBACKTONE_DR42	0x0	
#define	RINGBACKTONE_DR43	0x7d	
			
#define	RINGBACKPBXTONE_IR13	0x7870
#define	RINGBACKPBXTONE_IR14	0x007D	
#define	RINGBACKPBXTONE_IR16	0x7700	
#define	RINGBACKPBXTONE_IR17	0x0089	
#define	RINGBACKPBXTONE_DR32	0x1E	
#define	RINGBACKPBXTONE_DR33	0x1E	
#define	RINGBACKPBXTONE_DR36	0x40	
#define	RINGBACKPBXTONE_DR37	0x1f	
#define	RINGBACKPBXTONE_DR38	0xc0	
#define	RINGBACKPBXTONE_DR39	0x5d	
#define	RINGBACKPBXTONE_DR40	0x40	
#define	RINGBACKPBXTONE_DR41	0x1f	
#define	RINGBACKPBXTONE_DR42	0xc0	
#define	RINGBACKPBXTONE_DR43	0x5d	

#define	CONGESTIONTONE_IR13	0x7700
#define	CONGESTIONTONE_IR14	0x0089	
#define	CONGESTIONTONE_IR16	0x7120	
#define	CONGESTIONTONE_IR17	0x00B2	
#define	CONGESTIONTONE_DR32	0x1E	
#define	CONGESTIONTONE_DR33	0x1E	
#define	CONGESTIONTONE_DR36	0x40	
#define	CONGESTIONTONE_DR37	0x06	
#define	CONGESTIONTONE_DR38	0x60	
#define	CONGESTIONTONE_DR39	0x09	
#define	CONGESTIONTONE_DR40	0x40	
#define	CONGESTIONTONE_DR41	0x06	
#define	CONGESTIONTONE_DR42	0x60	
#define	CONGESTIONTONE_DR43	0x09	

#define	RINGBACKJAPANTONE_IR13	0X79C0	
#define	RINGBACKJAPANTONE_IR14	0xe9	
#define	RINGBACKJAPANTONE_IR16	0x7940	
#define	RINGBACKJAPANTONE_IR17	0xf2	
#define	RINGBACKJAPANTONE_DR32	0x1E	
#define	RINGBACKJAPANTONE_DR33	0x1E	
#define	RINGBACKJAPANTONE_DR36	0x40	
#define	RINGBACKJAPANTONE_DR37	0x1f	
#define	RINGBACKJAPANTONE_DR38	0x80
#define	RINGBACKJAPANTONE_DR39	0x3e	
#define	RINGBACKJAPANTONE_DR40	0x40	
#define	RINGBACKJAPANTONE_DR41	0x1f	
#define	RINGBACKJAPANTONE_DR42	0x80
#define	RINGBACKJAPANTONE_DR43	0x3e	

#define	BUSYJAPANTONE_IR13	0x79c0	
#define	BUSYJAPANTONE_IR14	0x00e9	
#define	BUSYJAPANTONE_IR16	0
#define	BUSYJAPANTONE_IR17	0	
#define	BUSYJAPANTONE_DR32	0x1E	
#define	BUSYJAPANTONE_DR33	0	
#define	BUSYJAPANTONE_DR36	0xa0	
#define	BUSYJAPANTONE_DR37	0x0f	
#define	BUSYJAPANTONE_DR38	0xa0
#define	BUSYJAPANTONE_DR39	0x0f
#define	BUSYJAPANTONE_DR40	0	
#define	BUSYJAPANTONE_DR41	0	
#define	BUSYJAPANTONE_DR42	0
#define	BUSYJAPANTONE_DR43	0	

#define	INIT_DR0	0X00	//	Serial Interface
#define	INIT_DR1	0X28	//	PCM Mode
#define	INIT_DR2	0X00	//	PCM TX Clock Slot Low Byte (1 PCLK cycle/LSB)
#define	INIT_DR3	0x00	//	PCM TX Clock Slot High Byte
#define	INIT_DR4	0x00	//	PCM RX Clock Slot Low Byte (1 PCLK cycle/LSB)
#define	INIT_DR5	0x00	//	PCM RX Clock Slot High Byte
#define	INIT_DR6	0x00	//	DIO Control (external battery operation, Si3211/12)
#define	INIT_DR8	0X00	//	Loopbacks (digital loopback default)
#define	INIT_DR9	0x00	//	Transmit and receive path gain and control
#define	INIT_DR10	0X28	//	Initialization Two-wire impedance (600  and enabled)
#define	INIT_DR11	0x33	//	Transhybrid Balance/Four-wire Return Loss
#define	INIT_DR14	0X10	//	Powerdown Control 1
#define	INIT_DR15	0x00	//	Initialization Powerdown Control 2
#define	INIT_DR18	0xff	//	Normal Oper. Interrupt Register 1 (clear with 0xFF)
#define	INIT_DR19	0xff	//	Normal Oper. Interrupt Register 2 (clear with 0xFF)
#define	INIT_DR20	0xff	//	Normal Oper. Interrupt Register 3 (clear with 0xFF)
#define	INIT_DR21	0xff	//	Interrupt Mask 1
#define	INIT_DR22	0xff	//	Initialization Interrupt Mask 2
#define	INIT_DR23	0xff	//	 Initialization Interrupt Mask 3
#define	INIT_DR32	0x00	//	Oper. Oscillator 1 Control梩one generation
#define	INIT_DR33	0x00	//	Oper. Oscillator 2 Control梩one generation
#define	INIT_DR34	0X18	//	34 0x22 0x00 Initialization Ringing Oscillator Control
#define	INIT_DR35	0x00	//	Oper. Pulse Metering Oscillator Control
#define	INIT_DR36	0x00	//	36 0x24 0x00 Initialization OSC1 Active Low Byte (125 祍/LSB)
#define	INIT_DR37	0x00	//	37 0x25 0x00 Initialization OSC1 Active High Byte (125 祍/LSB)
#define	INIT_DR38	0x00	//	38 0x26 0x00 Initialization OSC1 Inactive Low Byte (125 祍/LSB)
#define	INIT_DR39	0x00	//	39 0x27 0x00 Initialization OSC1 Inactive High Byte (125 祍/LSB)
#define	INIT_DR40	0x00	//	40 0x28 0x00 Initialization OSC2 Active Low Byte (125 祍/LSB)
#define	INIT_DR41	0x00	//	41 0x29 0x00 Initialization OSC2 Active High Byte (125 祍/LSB)
#define	INIT_DR42	0x00	//	42 0x2A 0x00 Initialization OSC2 Inactive Low Byte (125 祍/LSB)
#define	INIT_DR43	0x00	//	43 0x2B 0x00 Initialization OSC2 Inactive High Byte (125 祍/LSB)
#define	INIT_DR44	0x00	//	44 0x2C 0x00 Initialization Pulse Metering Active Low Byte (125 祍/LSB)
#define	INIT_DR45	0x00	//	45 0x2D 0x00 Initialization Pulse Metering Active High Byte (125 祍/LSB)
#define	INIT_DR46	0x00	//	46 0x2E 0x00 Initialization Pulse Metering Inactive Low Byte (125 祍/LSB)
#define	INIT_DR47	0x00	//	47 0x2F 0x00 Initialization Pulse Metering Inactive High Byte (125 祍/LSB)
#define	INIT_DR48	0X80	//	48 0x30 0x00 0x80 Initialization Ringing Osc. Active Timer Low Byte (2 s,125 祍/LSB)
#define	INIT_DR49	0X3E	//	49 0x31 0x00 0x3E Initialization Ringing Osc. Active Timer High Byte (2 s,125 祍/LSB)
#define	INIT_DR50	0X00	//	50 0x32 0x00 0x00 Initialization Ringing Osc. Inactive Timer Low Byte (4 s, 125 祍/LSB)
#define	INIT_DR51	0X7D	//	51 0x33 0x00 0x7D Initialization Ringing Osc. Inactive Timer High Byte (4 s, 125 祍/LSB)
#define	INIT_DR52	0X00	//	52 0x34 0x00 Normal Oper. FSK Data Bit
#define	INIT_DR63	0X54	//	63 0x3F 0x54 Initialization Ringing Mode Loop Closure Debounce Interval
#define	INIT_DR64	0x00	//	64 0x40 0x00 Normal Oper. Mode Byte梡rimary control
#define	INIT_DR65	0X61	//	65 0x41 0x61 Initialization External Bipolar Transistor Settings
#define	INIT_DR66	0X03	//	66 0x42 0x03 Initialization Battery Control
#define	INIT_DR67	0X1F	//	67 0x43 0x1F Initialization Automatic/Manual Control
#define	INIT_DR69	0X0C	//	69 0x45 0x0A 0x0C Initialization Loop Closure Debounce Interval (1.25 ms/LSB)
#define	INIT_DR70	0X0A	//	70 0x46 0x0A Initialization Ring Trip Debounce Interval (1.25 ms/LSB)
#define	INIT_DR71	0X01	//	71 0x47 0x00 0x01 Initialization Off-Hook Loop Current Limit (20 mA + 3 mA/LSB)
#define	INIT_DR72	0X20	//	72 0x48 0x20 Initialization On-Hook Voltage (open circuit voltage) = 48 V(1.5 V/LSB)
#define	INIT_DR73	0X02	//	73 0x49 0x02 Initialization Common Mode Voltage梀CM =