s12_pim.h

MC9S12C32 LIN-BUS源码（编译环境：CodeWarriorV3.1）

  }tPIFH;

#define PIFH0	0x01	/*bit masks */
#define PIFH1	0x02
#define PIFH2 	0x04
#define PIFH3 	0x08
#define PIFH4 	0x10
#define PIFH5 	0x20
#define PIFH6 	0x40
#define PIFH7 	0x80


/******************************  PORT J  **************************/

typedef union uPTJ		/*i/o register */
  {
  tU08	byte;
  struct
    {
    tU08 ptj0	:1;		/*i/o port pins */
    tU08 ptj1	:1;
    tU08 ptj2	:1;
    tU08 ptj3	:1;
    tU08 ptj4	:1;
    tU08 ptj5	:1;
    tU08 ptj6	:1;
    tU08 ptj7	:1;
    }bit;
  }tPTJ;

#define PTJ0	0x01	/*bit masks */
#define PTJ1	0x02
#define PTJ2 	0x04
#define PTJ3 	0x08
#define PTJ4 	0x10
#define PTJ5 	0x20
#define PTJ6 	0x40
#define PTJ7 	0x80

typedef union uPTIJ		/*input register */
  {
  tU08	byte;
  struct
    {
    tU08 ptij0	:1;		/*i/o port pins */
    tU08 ptij1	:1;
    tU08 ptij2	:1;
    tU08 ptij3	:1;
    tU08 ptij4	:1;
    tU08 ptij5	:1;
    tU08 ptij6	:1;
    tU08 ptij7	:1;
    }bit;
  }tPTIJ;

#define PTIJ0	0x01	/*bit masks */
#define PTIJ1	0x02
#define PTIJ2 	0x04
#define PTIJ3 	0x08
#define PTIJ4 	0x10
#define PTIJ5 	0x20
#define PTIJ6 	0x40
#define PTIJ7 	0x80

typedef union uDDRJ		/*data direction register */
  {
  tU08	byte;
  struct
    {
    tU08 ddrj0	:1;		/*data direction bits (0:input;1:output) */
    tU08 ddrj1	:1;
    tU08 ddrj2	:1;
    tU08 ddrj3	:1;
    tU08 ddrj4	:1;
    tU08 ddrj5	:1;
    tU08 ddrj6	:1;
    tU08 ddrj7	:1;
    }bit;
  }tDDRJ;

#define DDRJ0	0x01	/*bit masks */
#define DDRJ1	0x02
#define DDRJ2	0x04
#define DDRJ3	0x08
#define DDRJ4	0x10
#define DDRJ5	0x20
#define DDRJ6	0x40
#define DDRJ7	0x80

typedef union uRDRJ		/*reduced drive register */
  {
  tU08	byte;
  struct
    {
    tU08 rdrj0	:1;		/*reduced drive bits (0:full;1:reduced) */
    tU08 rdrj1	:1;
    tU08 rdrj2	:1;
    tU08 rdrj3	:1;
    tU08 rdrj4	:1;
    tU08 rdrj5	:1;
    tU08 rdrj6	:1;
    tU08 rdrj7	:1;
    }bit;
  }tRDRJ;

#define RDRJ0	0x01	/*bit masks */
#define RDRJ1	0x02
#define RDRJ2	0x04
#define RDRJ3	0x08
#define RDRJ4	0x10
#define RDRJ5	0x20
#define RDRJ6	0x40
#define RDRJ7	0x80

typedef union uPERJ		/*pull-up/dn enable register */
  {
  tU08	byte;
  struct
    {
    tU08 perj0	:1;		/*pull-up/dn bits (1:enabled) */
    tU08 perj1	:1;
    tU08 perj2	:1;
    tU08 perj3	:1;
    tU08 perj4	:1;
    tU08 perj5	:1;
    tU08 perj6	:1;
    tU08 perj7	:1;
    }bit;
  }tPERJ;

#define PERJ0	0x01	/*bit masks */
#define PERJ1	0x02
#define PERJ2 	0x04
#define PERJ3 	0x08
#define PERJ4 	0x10
#define PERJ5 	0x20
#define PERJ6 	0x40
#define PERJ7 	0x80

typedef union uPPSJ		/*pull-up/dn polarity register */
  {
  tU08	byte;
  struct
    {
    tU08 ppsj0	:1;		/*pull-up/dn bits (0:pull-up;1:pull-dn) */
    tU08 ppsj1	:1;
    tU08 ppsj2	:1;
    tU08 ppsj3	:1;
    tU08 ppsj4	:1;
    tU08 ppsj5	:1;
    tU08 ppsj6	:1;
    tU08 ppsj7	:1;
    }bit;
  }tPPSJ;

#define PPSJ0	0x01	/*bit masks */
#define PPSJ1	0x02
#define PPSJ2 	0x04
#define PPSJ3 	0x08
#define PPSJ4 	0x10
#define PPSJ5 	0x20
#define PPSJ6 	0x40
#define PPSJ7 	0x80

typedef union uPIEJ		/*interrupt enable register */
  {
  tU08	byte;
  struct
    {
    tU08 piej0	:1;		/*interrupt source (1:enabled) */
    tU08 piej1	:1;
    tU08 piej2	:1;
    tU08 piej3	:1;
    tU08 piej4	:1;
    tU08 piej5	:1;
    tU08 piej6	:1;
    tU08 piej7	:1;
    }bit;
  }tPIEJ;

#define PIEJ0	0x01	/*bit masks */
#define PIEJ1	0x02
#define PIEJ2 	0x04
#define PIEJ3 	0x08
#define PIEJ4 	0x10
#define PIEJ5 	0x20
#define PIEJ6 	0x40
#define PIEJ7 	0x80

typedef union uPIFJ		/*wired-or mode register */
  {
  tU08	byte;
  struct
    {
    tU08 pifj0	:1;		/*wired-or bits (1:enabled) */
    tU08 pifj1	:1;
    tU08 pifj2	:1;
    tU08 pifj3	:1;
    tU08 pifj4	:1;
    tU08 pifj5	:1;
    tU08 pifj6	:1;
    tU08 pifj7	:1;
    }bit;
  }tPIFJ;

#define PIFJ0	0x01	/*bit masks */
#define PIFJ1	0x02
#define PIFJ2 	0x04
#define PIFJ3 	0x08
#define PIFJ4 	0x10
#define PIFJ5 	0x20
#define PIFJ6 	0x40
#define PIFJ7 	0x80

/* definitions for C32 */

typedef union uPTAD		/*port AD i/o register */
  {
  tU08	byte;
  struct
    {
    tU08 ptad0	:1;		
    tU08 ptad1	:1;
    tU08 ptad2	:1;
    tU08 ptad3	:1;
    tU08 ptad4	:1;
    tU08 ptad5	:1;
    tU08 ptad6	:1;
    tU08 ptad7	:1;
    }bit;
  }tPTAD;

#define PTAD0	0x01	/*bit masks */
#define PTAD1	0x02
#define PTAD2 	0x04
#define PTAD3 	0x08
#define PTAD4 	0x10
#define PTAD5 	0x20
#define PTAD6 	0x40
#define PTAD7 	0x80


typedef union uPTIAD		/*port AD input register */
  {
  tU08	byte;
  struct
    {
    tU08 ptiad0	:1;		
    tU08 ptiad1	:1;
    tU08 ptiad2	:1;
    tU08 ptiad3	:1;
    tU08 ptiad4	:1;
    tU08 ptiad5	:1;
    tU08 ptiad6	:1;
    tU08 ptiad7	:1;
    }bit;
  }tPTIAD;

#define PTIAD0	0x01	/*bit masks */
#define PTIAD1	0x02
#define PTIAD2 	0x04
#define PTIAD3 	0x08
#define PTIAD4 	0x10
#define PTIAD5 	0x20
#define PTIAD6 	0x40
#define PTIAD7 	0x80


typedef union uDDRAD		/*port AD data direction register */
  {
  tU08	byte;
  struct
    {
    tU08 ddrad0	:1;		
    tU08 ddrad1	:1;
    tU08 ddrad2	:1;
    tU08 ddrad3	:1;
    tU08 ddrad4	:1;
    tU08 ddrad5	:1;
    tU08 ddrad6	:1;
    tU08 ddrad7	:1;
    }bit;
  }tDDRAD;

#define DDRAD0	0x01		/*bit masks */
#define DDRAD1	0x02
#define DDRAD2 	0x04
#define DDRAD3 	0x08
#define DDRAD4 	0x10
#define DDRAD5 	0x20
#define DDRAD6 	0x40
#define DDRAD7 	0x80


typedef union uRDRAD		/*port AD reduced drive register */
  {
  tU08	byte;
  struct
    {
    tU08 rdrad0	:1;		
    tU08 rdrad1	:1;
    tU08 rdrad2	:1;
    tU08 rdrad3	:1;
    tU08 rdrad4	:1;
    tU08 rdrad5	:1;
    tU08 rdrad6	:1;
    tU08 rdrad7	:1;
    }bit;
  }tRDRAD;

#define RDRAD0	0x01		/*bit masks */
#define RDRAD1	0x02
#define RDRAD2 	0x04
#define RDRAD3 	0x08
#define RDRAD4 	0x10
#define RDRAD5 	0x20
#define RDRAD6 	0x40
#define RDRAD7 	0x80								
     

typedef union uPERAD		/*port AD pull device enable register */
  {
  tU08	byte;
  struct
    {
    tU08 perad0	:1;		
    tU08 perad1	:1;
    tU08 perad2	:1;
    tU08 perad3	:1;
    tU08 perad4	:1;
    tU08 perad5	:1;
    tU08 perad6	:1;
    tU08 perad7	:1;
    }bit;
  }tPERAD;

#define PERAD0	0x01		/*bit masks */
#define PERAD1	0x02
#define PERAD2 	0x04
#define PERAD3 	0x08
#define PERAD4 	0x10
#define PERAD5 	0x20
#define PERAD6 	0x40
#define PERAD7 	0x80	

 	
 typedef union uPPSAD		/*port AD pull device enable register */
  {
  tU08	byte;
  struct
    {
    tU08 ppsad0	:1;		
    tU08 ppsad1	:1;
    tU08 ppsad2	:1;
    tU08 ppsad3	:1;
    tU08 ppsad4	:1;
    tU08 ppsad5	:1;
    tU08 ppsad6	:1;
    tU08 ppsad7	:1;
    }bit;
  }tPPSAD;

#define PPSAD0	0x01		/*bit masks */
#define PPSAD1	0x02
#define PPSAD2 	0x04
#define PPSAD3 	0x08
#define PPSAD4 	0x10
#define PPSAD5 	0x20
#define PPSAD6 	0x40
#define PPSAD7 	0x80		

/* end definitions for C32 */

#ifndef S12C32	/* structure for all HCS12 devices except S12C32 */

typedef struct					/*port integration module  */
  {
								/*PORT T */
  volatile tPTT		ptt;		/*i/o register */
  volatile tPTIT	ptit;		/*input register */
  volatile tDDRT	ddrt;		/*data direction register */
  volatile tRDRT	rdrt;		/*reduced drive register */
  volatile tPERT	pert;		/*pull-up/dn enable register */
  volatile tPPST	ppst;		/*pull-up/dn polarity register */
           tU08		rsvt[2];	/*reserved (maintaining memory map) */

  								/*PORT S */
  volatile tPTS		pts;		/*i/o register */
  volatile tPTIS	ptis;		/*input register */
  volatile tDDRS	ddrs;		/*data direction register */
  volatile tRDRS	rdrs;		/*reduced drive register */
  volatile tPERS	pers;		/*pull-up/dn enable register */
  volatile tPPSS	ppss;		/*pull-up/dn polarity register */
  volatile tWOMS	woms;		/*wired-or mode register */
           tU08		rsvs;		/*reserved (maintaining memory map) */

								/*PORT M */
  volatile tPTM		ptm;		/*i/o register */
  volatile tPTIM	ptim;		/*input register */
  volatile tDDRM	ddrm;		/*data direction register */
  volatile tRDRM	rdrm;		/*reduced drive register */
  volatile tPERM	perm;		/*pull-up/dn enable register */
  volatile tPPSM	ppsm;		/*pull-up/dn polarity register */
  volatile tWOMM	womm;		/*wired-or mode register */
  volatile tMODRR	modrr;		/*module routing register */

  								/*PORT P */
  volatile tPTP		ptp;		/*i/o register */
  volatile tPTIP	ptip;		/*input register */
  volatile tDDRP	ddrp;		/*data direction register */
  volatile tRDRP	rdrp;		/*reduced drive register */
  volatile tPERP	perp;		/*pull-up/dn enable register */
  volatile tPPSP	ppsp;		/*pull-up/dn polarity register */
  volatile tPIEP	piep;		/*interrupt enable register */
  volatile tPIFP	pifp;		/*interrupt flag register */

  								/*PORT H */
  volatile tPTH		pth;		/*i/o register */
  volatile tPTIH	ptih;		/*input register */
  volatile tDDRH	ddrh;		/*data direction register */
  volatile tRDRH	rdrh;		/*reduced drive register */
  volatile tPERH	perh;		/*pull-up/dn enable register */
  volatile tPPSH	ppsh;		/*pull-up/dn polarity register */
  volatile tPIEH	pieh;		/*interrupt enable register */
  volatile tPIFH	pifh;		/*interrupt flag register */

  								/*PORT J */
  volatile tPTJ		ptj;		/*i/o register */
  volatile tPTIJ	ptij;		/*input register */
  volatile tDDRJ	ddrj;		/*data direction register */
  volatile tRDRJ	rdrj;		/*reduced drive register */
  volatile tPERJ	perj;		/*pull-up/dn enable register */
  volatile tPPSJ	ppsj;		/*pull-up/dn polarity register */
  volatile tPIEJ	piej;		/*interrupt enable register */
  volatile tPIFJ	pifj;		/*interrupt flag register */
  } tPIM;
  
  #else  						/* structure for S12C32 */
  
  typedef struct				/*port integration module  */
  {
								/*PORT T */
  volatile tPTT		ptt;		/*i/o register */
  volatile tPTIT	ptit;		/*input register */
  volatile tDDRT	ddrt;		/*data direction register */
  volatile tRDRT	rdrt;		/*reduced drive register */
  volatile tPERT	pert;		/*pull-up/dn enable register */
  volatile tPPST	ppst;		/*pull-up/dn polarity register */
           tU08		rsvt;		/*reserved (maintaining memory map) */
  volatile tMODRR   modrr;		/*port T module routing register */	
  						
  								/*PORT S */
  volatile tPTS		pts;		/*i/o register */
  volatile tPTIS	ptis;		/*input register */
  volatile tDDRS	ddrs;		/*data direction register */
  volatile tRDRS	rdrs;		/*reduced drive register */
  volatile tPERS	pers;		/*pull-up/dn enable register */
  volatile tPPSS	ppss;		/*pull-up/dn polarity register */
  volatile tWOMS	woms;		/*wired-or mode register */
  volatile tU08		rsvs1;		/*reserved (maintaining memory map) */

								/*PORT M */
  volatile tPTM		ptm;		/*i/o register */
  volatile tPTIM	ptim;		/*input register */
  volatile tDDRM	ddrm;		/*data direction register */
  volatile tRDRM	rdrm;		/*reduced drive register */
  volatile tPERM	perm;		/*pull-up/dn enable register */
  volatile tPPSM	ppsm;		/*pull-up/dn polarity register */
  volatile tWOMM	womm;		/*wired-or mode register */
  volatile tU08	    rsvs2;		/*reserved (maintaining memory map) */

  								/*PORT P */
  volatile tPTP		ptp;		/*i/o register */
  volatile tPTIP	ptip;		/*input register */
  volatile tDDRP	ddrp;		/*data direction register */
  volatile tRDRP	rdrp;		/*reduced drive register */
  volatile tPERP	perp;		/*pull-up/dn enable register */
  volatile tPPSP	ppsp;		/*pull-up/dn polarity register */
  volatile tPIEP	piep;		/*interrupt enable register */
  volatile tPIFP	pifp;		/*interrupt flag register */

  volatile tU08 	rsvs3[8];	/*reserved (maintaining memory map) */ 
  
  								/*PORT J */
  volatile tPTJ		ptj;		/*i/o register */
  volatile tPTIJ	ptij;		/*input register */
  volatile tDDRJ	ddrj;		/*data direction register */
  volatile tRDRJ	rdrj;		/*reduced drive register */
  volatile tPERJ	perj;		/*pull-up/dn enable register */
  volatile tPPSJ	ppsj;		/*pull-up/dn polarity register */
  volatile tPIEJ	piej;		/*interrupt enable register */
  volatile tPIFJ	pifj;		/*interrupt flag register */
  
  								/*PORT AD */
  volatile tPTAD    ptad;		/*port AD i/o register */
  volatile tPTIAD   ptiad;		/*port AD input register */
  volatile tDDRAD   ddrad;      /*port AD data direction register */
  volatile tRDRAD   rdrad;      /*port AD reduced drive register */
  volatile tPERAD   perad; 		/*port AD pull device enable register */
  volatile tPPSAD   ppsad;      /*port AD polarity select register */

  volatile tU08   	rsvs4[10];  /*reserved (maintaining memory map) */ 
 
  }tPIM;
  #endif /*S12C32 */	

#endif /*S12_PIM_H */