📄 target.h
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/* ************************************************************************ *
* *
* Volcano Communications technologies AB *
* All rights reserved *
* *
* ************************************************************************ */
/* ************************************************************************ *
* File: target.h *
* Description: Target specific definitions/structures for the Hiware *
* HC08ESCI *
* LTP example application *
* *
* ************************************************************************ */
#ifndef __TARGET_H__
#define __TARGET_H__
#include <lin.h>
#include <MC68HC908GZ60.h>
typedef volatile unsigned char creg_u8;
typedef volatile unsigned short creg_u16;
/* Volcano processing period is 5 ms in this application. Value given in
* number of microseconds. The busy_wait routine fails if PERIOD is
* greater than 32767, i.e. don't use processing periods longer than 32 ms. */
// #define PERIOD (6144u) /* # wait 5 ms Mon08 Cyclone clock used. Timer Prescaler also changed */
/* # used when Mon08Cyclone clock is used */
#define PERIOD (5000u) /* # Wait 5 ms internal clock used */
/* # used when 8MHz clock source is used */
#define HW_DELAY PERIOD
#define HC908GZ60
#ifdef HC08AZ60
/* Modulo timer (TIM) module */
#define TIMERSC (*(creg_u8 *)0x4bu) /* TIM Status and control register */
#define INITTIMER ((l_u8)0x12u)
#define TIMERCNT (*(creg_u16 *)0x4cu) /* Counter */
#define COP (*(volatile l_u8*)0xffff) /* Watch-dog */
#endif
#ifdef HC908GZ60
/* Port, Enable LIN tranciever */
/* Modulo timer (TIM) module */
#define TIMERSC T1SC /* TIM Status and control register */
// #define INITTIMER ((l_u8)0x12u) /* # used when Mon08Cyclone clock is used */
#define INITTIMER ((l_u8)0x11u) /* # used when 8MHz clock source is used */
/* # prescaler value of 4 when Mon08Cyclone clock is used */
/* # prescaler value of 2 when 8Mhz clock source is used */
#define TIMERCNTH T1CNTH /* Counter */
#define TIMERCNTL T1CNTL /* Counter */
#define TIMERMOD T1MOD
#define COP COPCTL /* Watch-dog */
#endif
#define LSB(x) ((l_u8)x)
#define MSB(x) ((l_u8)(x>>8))
/* This is a target dependent macro that should enable interrupts. Using
* v_sys_irq_restore() is just one way of doing it, which works for this
* target. */
#define ENABLE_INTS() l_sys_irq_restore((l_irqmask)0)
#define DISABLE_INTS() l_sys_irq_disable()
/* Reset Watch-dog counter */
#define PET_WATCHDOG() (COP = (l_u8)0)
/* Interrupt handling, vectab.asm contains the vector table */
#define UART_0_RX_INTERRUPT_HANDLER interrupt 13 void uart_0_rx_handler(void)
/* Function prototypes */
extern void init_environment (void);
/* ************************************************************************
* Perform initialisation of target. Initialise a free running counter at
* 1Mhz.
*/
void init_target (void);
/* ************************************************************************
* Read timer channel A (free running counter at 1Mhz) and return current
* value.
*/
l_u16 l_get_us_counter (void);
/* ************************************************************************
* Restores interrupt level to the previous level, as indicated by the in-
* put previous. On the CPU12 family the interrupt level can only be either
* "interrupts enabled" or "interrupts disabled".
*/
void l_sys_irq_restore (l_irqmask previous);
/* ************************************************************************
* Disable interrupts, and return the previous value of the interrupt
* level.
*/
l_irqmask l_sys_irq_disable(void);
#endif /* __TARGET_H__ */
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