📄 target.h
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/* ************************************************************************ *
* *
* Volcano Communications technologies AB *
* All rights reserved *
* *
* ************************************************************************ */
/* ************************************************************************ *
* File: target.h *
* Description: Target specific definitions/structures for the Hiware *
* HC08ESCI *
* LTP example application *
* *
* ************************************************************************ */
#ifndef __TARGET_H__
#define __TARGET_H__
#include <lin.h>
#include <MC68HC908EY16.h>
typedef volatile unsigned char creg_u8;
typedef volatile unsigned short creg_u16;
#define BIT0 (((l_u8)1u)<<0)
#define BIT1 (((l_u8)1u)<<1)
#define BIT2 (((l_u8)1u)<<2)
#define BIT3 (((l_u8)1u)<<3)
#define BIT4 (((l_u8)1u)<<4)
#define BIT5 (((l_u8)1u)<<5)
#define BIT6 (((l_u8)1u)<<6)
#define BIT7 (((l_u8)1u)<<7)
#define HC08EY
#define BUS_CLOCK 4070ul
/* Volcano processing period is 5 ms in this application. Value given in
* number of microseconds. The busy_wait routine fails if PERIOD is
* greater than 32767, i.e. don't use processing periods longer than 32 ms. */
/* Timer input clock in kHz */
#define TIMER_CLK BUS_CLOCK
/* Timer CLK will be divided by this value (using prescaler). */
#define TIMER_DIVIDER 4ul
/* The required processing period im uS. */
#define PERIOD (5000ul)
/* Result. (How many ticks does we have to count in order to get PERIOD long delay. ) */
#define HW_DELAY ((PERIOD*TIMER_CLK)/(1000ul*TIMER_DIVIDER))
/* Timer A (TIMA) module */
/* Prescaler selection bits*/
#define TASC_PS_MASK ((l_u8) 7u)
/* Prescaler value (Divide BUS clock by 4 (timer runs from CGMXCLK /4; assuming CGMXCLK ~ 16MHZ))*/
#define TASC_PS_VALUE ((l_u8) 0x2u)
/* Timer counter register */
#define TACNTW ((*(creg_u8 *) 0x21 << 8) | (*(creg_u8 *) 0x22))
/* Computer operates properly module. */
#define COP COPCTL /* Watch-dog */
/* ESCI baudrate source select bit. */
#define ESCIBD_SRC BIT6
/* This is a target dependent macro that should enable interrupts. Using
* v_sys_irq_restore() is just one way of doing it, which works for this
* target. */
#define ENABLE_INTS() asm cli;
#define DISABLE_INTS() asm sei;
/* Reset Watch-dog counter */
#define PET_WATCHDOG() (COP = (l_u8) 0u)
/* Interrupt handling, vectab.asm contains the vector table */
#define UART_0_RX_INTERRUPT_HANDLER interrupt 11 void uart_0_rx_handler(void)
/* These macro definitions can be used to help debugging. */
#define SYNC_PIN 1 << 2
#define INIT_SYNC_PIN() (DDRA = 0x2)
#define TOGGLE_SYNC() (PTA ^= 0x2)
/* Function prototypes */
/* ************************************************************************
* Adjusts CPU internal clock generator based on bit-time measurements done
* by the LTP.
*/
#define ADJUST_CLOCK() adjust_clock()
extern void adjust_clock(void);
/* ************************************************************************
* Perform initialisation of development system (if any)
*/
extern void init_environment (void);
/* ************************************************************************
* Perform initialisation of target. Initialise a free running counter at
* 1MHz.
*/
void init_target (void);
/* ************************************************************************
* Read timer channel A (free running counter at 1MHz) and return current
* value.
*/
l_u16 l_get_us_counter (void);
/* ************************************************************************
* Restores interrupt level to the previous level, as indicated by the in-
* put previous. On the CPU12 family the interrupt level can only be either
* "interrupts enabled" or "interrupts disabled".
*/
void l_sys_irq_restore (l_irqmask previous);
/* ************************************************************************
* Disable interrupts, and return the previous value of the interrupt
* level.
*/
l_irqmask l_sys_irq_disable(void);
#endif /* __TARGET_H__ */
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