📄 the i2c layer protocol.htm
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<H2>The I2C protocol</H2>
<DIV>References:<BR>Philips Semiconductors, "The I2C-Bus Specification?Version
2.1," January 2000, <A
href="http://www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf"
target=_top>http://www.semiconductors.philips.com/acrobat/literature/9398/39340011.pdf</A>.<BR>Documentation/i2c/i2c-protocol<BR><A
href="http://www.esacademy.com/faq/i2c/general/i2cproto.htm"
target=_top>http://www.esacademy.com/faq/i2c/general/i2cproto.htm</A><BR></DIV><BR
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<DIV>The I2C bus consists of two active bidirectional wires, besides the ground
wire. One wire carries the data SDA (Serial Data), the other is for clock SCL
(Serial Click Line). Every device on the bus has its own address, and can act as
a receiver and a transmitter (although some devices act only as one of the two).
</DIV>
<DIV>The bus is multi-master: more than one IC capable of initiating a data
transfer can be connected to it. The IC that starts the transfer is the bus
master, the other become the bus slaves. The master issues a START (pull SDA,
then pull SCL) to signal the beginning of a transfer. The end of the transfer
will be signalled with a STOP (release SCL, then release SDA ). Then the master
sends one byte containing the address of the ather part and a read/write flag:
bits are send MSB first, LSB last; the seven most significant bits are the
address, the LSB is the flag (0 for WRITE). Bits are sent on the SDA line, one
bit for each clock pulse (SCL). Some addresses are reserved: <PRE> 0000-000(0) general call
0000-000(1) START byte
0000-001(x) C-bus (obsolete)
0000-010(x) a different bus
0000-011(x) future
0000-1xx(x) future
1111-1xx(x) future
1111-0xx(x) 10-bit slave addressing
</PRE>EXtended address mode (10-bit addresses) has a two-byte address. The first
byte contains the two most significant bits of the address and the r/w flag. The
second byte contains the other eight bits. </DIV>
<DIV>Slaves respond to an address byte that matches and to a data byte (it they
are being addressed) with an ACK: pull SDA, and when the master has issued the
next SCL clock pulse, release SDA. </DIV>
<DIV>To receive a byte from the slave, the master must send eight clock pulses
(on SCL) while the slave writes the bits on the SDA (high for 1, low for 0).
Before all the master releases tha SDA and the slaves takes control of it. Then
the master pulses the SCL; when it is high it read the bit from SDA. </DIV><BR
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