📄 uart.h
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/*
****************************************Copyright (c)**************************************************
** 广州周立功单片机发展有限公司
** 研 究 所
** CAN开发组
**
** http://www.zlgmcu.com
**
**--------------文件信息--------------------------------------------------------------------------------
**文 件 名: UART.H
**创 建 人: 滕欣欣
**最后修改日期: 2004年5月01日
**描 述: UART的基本寄存器和操作函数声明
**
********************************************************************************************************
*/
#ifndef _UART_H_
#define _UART_H_
#ifndef _UART_GLOBAL_
#define UART_GLOBAL extern
#else
#define UART_GLOBAL
#endif
#define UART_OFFSET_ADR 0x4000
#define UARTRBR_BADR 0xE000C000
#define UARTTHR_BADR 0xE000C000
#define UARTDLL_BADR 0xE000C000
#define UARTDLM_BADR 0xE000C004
#define UARTIER_BADR 0xE000C004
#define UARTIIR_BADR 0xE000C008
#define UARTFCR_BADR 0xE000C008
#define UARTLCR_BADR 0xE000C00C
#define UARTLSR_BADR 0xE000C014
/*
************************************
应用变量声明
************************************
*/
/*
************************************
UART通道枚举
************************************
*/
typedef enum _uartnum_
{
UART0 = 0,
UART1
}eUARTNUM;
/*
******************************
** UART寄存器定义
******************************
*/
/*
**************************************************************************
** 定义 UARTRBR 寄存器 (RO)
**Receiver Buffer Register ((DLAB = 0)
**************************************************************************
*/
typedef struct _uartrbr_
{
INT32U WritedData :8;
INT32U Reserve :24;
}stcUARTRBR,*P_stcUARTRBR;
#define UARTRBR(UARTNum) (*((volatile P_stcUARTRBR)(UARTRBR_BADR + UARTNum* UART_OFFSET_ADR)))
/*
**************************************************************************
** 定义 UARTTHR 寄存器 (WO)
**UART0 Transmitter Holding Register (DLAB = 0)
**************************************************************************
*/
typedef struct _uartthr_
{
INT32U WritedData :8;
INT32U Reserve :24;
}stcUARTTHR,*P_stcUARTTHR;
#define UARTTHR(UARTNum) (*((volatile P_stcUARTTHR)(UARTTHR_BADR + UARTNum* UART_OFFSET_ADR)))
/*
**************************************************************************
** 定义 UARTDLL 寄存器 (RW)
**Divisor Latch LSB Register (DLAB = 1)
**************************************************************************
*/
typedef struct _uartdll_
{
INT32U DLL :8;
INT32U Reserve :24;
}stcUARTDLL,*P_stcUARTDLL;
#define UARTDLL(UARTNum) (*((volatile P_stcUARTDLL)(UARTDLL_BADR + UARTNum* UART_OFFSET_ADR)))
/*
**************************************************************************
** 定义 UARTDLM 寄存器 (RW)
**Divisor Latch MSB Register ( (DLAB = 1)
**************************************************************************
*/
typedef struct _uartdlm_
{
INT32U DLM :8;
INT32U Reserve :24;
}stcUARTDLM,*P_stcUARTDLM;
#define UARTDLM(UARTNum) (*((volatile P_stcUARTDLM)(UARTDLM_BADR + UARTNum* UART_OFFSET_ADR)))
/*
**************************************************************************
** 定义 UARTIER 寄存器 (R/W)
**The UARTIER is used to enable the four UART interrupt sources.(DLAB = 0)
**************************************************************************
*/
typedef struct _uartier_
{
INT32U ERxDA :1; //Enable Rx Data Available nterrupt
INT32U ETHRE :1; //Enable THRE Interrupt
INT32U ERxLS :1; //Enable Rx Line Status Interrupt
//////////////////////
// UART1 ONLY //
//////////////////////
INT32U EMS :1; //Enable Modem Status Interrupt
INT32U Reserve :28;
}stcUARTIER,*P_stcUARTIER;
#define UARTIER(UARTNum) (*((volatile P_stcUARTIER)(UARTIER_BADR + UARTNum* UART_OFFSET_ADR)))
/*
**************************************************************************
** 定义 UARTIIR 寄存器 (RO)
**The UARTIIR provides a status code that denotes the priority and source of
**a pending interrupt. The interrupts are frozen during an U0IIR access.
**If an interrupt occurs during an UARTIIR access, the interrupt is recorded
**for the next UARTIIR access.
**************************************************************************
*/
typedef struct _uartiir_
{
INT32U IntPd :1; //0: At least one interrupt is pending.
//1: No pending interrupts.
INT32U IId :3; //011: 1. Receive Line Status (RLS)
//010: 2a.Receive Data Available (RDA)
//110: 2b.Character Time-out Indicator (CTI)
//001: 3. THRE Interrupt.
INT32U RSV_BIT_1 :2;
INT32U FIFO :2; //These bits are equivalent to UxFCR0.
INT32U Reserve :24;
}stcUARTIIR,*P_stcUARTIIR;
#define UARTIIR(UARTNum) (*((volatile P_stcUARTIIR)(UARTIIR_BADR + UARTNum* UART_OFFSET_ADR)))
/*
**************************************************************************
** 定义 UARTFCR 寄存器(WO)
**The UARTFCR controls the operation of the UART Rx and Tx FIFOs.
**************************************************************************
*/
typedef union _uartfcr_
{
INT32U EFIFO :1; //Active high enable for both UART Rx and Tx FIFOs and UFCR7:1 access.
//This bit must be set for proper UART0 opearation.Any transition on
//this bit will automatically clear the UART FIFOs.
INT32U RxFIFO :1; //Writing a logic 1 to UxFCR1 will clear all bytes in UART Rx FIFO and
//reset the pointer logic. This bit is self-clearing.
INT32U TxFIFO :1; //Writing a logic 1 to UxFCR2 will clear all bytes in UART Tx FIFO and
//reset the pointer logic. This bit is self-clearing.
INT32U RSV_BIT_1 :3; //
INT32U RxTLS :2; //00: trigger level 0 (default= 1)
//01: trigger level 1 (default= 4)
//10: trigger level 2 (default= 8)
//11: trigger level 3 (default= 14)
//These two bits determine how many receiver UART FIFO characters must be written
//before an interrupt is activated. The four trigger levels are defined by the user at
//compilation allowing the user to tune the trigger levels to the FIFO depths chosen.
INT32U Reserve :24;
}stcUARTFCR,*P_stcUARTFCR;
#define UARTFCR(UARTNum) (*((volatile P_stcUARTFCR)(UARTFCR_BADR + UARTNum* UART_OFFSET_ADR)))
/*
**************************************************************************
** 定义 UARTLCR 寄存器(R/W)
**The UARTLCR determines the format of the data character that is to be
**transmitted or received.
**************************************************************************
*/
typedef struct _uartlcr_
{
INT32U WordLen :2; //00: 5 bit character length
//01: 6 bit character length
//10: 7 bit character length
//11: 8 bit character length
INT32U Stop :1; //0: 1 stop bit
//1: 2 stop bits (1.5 if UARTLCR[1:0]=00)
INT32U ParityEnable :1; //0: Disable parity generation and checking
//1: Enable parity generation and checking
INT32U ParityMode :2; //00: Odd parity
//01: Even parity
//10: Forced “1” stick parity
//11: Forced “0” stick parity
INT32U BreakEnable :1; //0: Disable break transmission
//1: Enable break transmission.
//Output pin UART0 TxD is forced to logic 0 when U0LCR6 is active high.
INT32U DLABAcceEn :1; //0: Disable access to Divisor Latches
//1: Enable access to Divisor Latches
INT32U Reserve :24;
}stcUARTLCR, *P_stcUARTLCR;
#define UARTLCR(UARTNum) (*((volatile P_stcUARTLCR)(UARTLCR_BADR + UARTNum* UART_OFFSET_ADR)))
/*
**************************************************************************
** 定义 UARTLSR 寄存器(RO)
**The U0LSR is a read-only register that provides status information
**on the UART0 Tx and Rx blocks.
**************************************************************************
*/
typedef struct _uartlsr_
{
INT32U RDR :1; //0: U0RBR is empty
//1: U0RBR contains valid
INT32U OE :1; //0: Overrun error state is inactive.
//1: Overrun error state is active.
INT32U PE :1; //0: Parity error state is inactive.
//1: Parity error status is active.
INT32U FE :1; //0: Framing error state is inactive.
//1: Framing error state is active.
INT32U BI :1; //0: Break interrupt state is inactive.
//1: Break interrupt state is active.
INT32U THRE :1; //0: U0THR contains valid data.
//1: U0THR is empty.
INT32U TEMT :1; //0: U0THR and/or the U0TSR contains valid data.
//1: U0THR and the U0TSR are empty.
INT32U RXFE:1; //0: U0RBR contains no UART0 Rx errors or U0FCR0=0.
//1: UART0 RBR contains at least one UART0 Rx error.
INT32U RSV_BIT :24;
}stcUARTLSR,*P_stcUARTLSR;
#define UARTLSR(UARTNum) (*((volatile P_stcUARTLSR)(UARTLSR_BADR + UARTNum* UART_OFFSET_ADR)))
/*
****************************************
** UART基本函数声明
****************************************
*/
/*
*********************************************************************************************************
** 函数名称: void UARTInit (eUARTNUM UARTNum)
** 全局变量: 无
** 作 者: 滕欣欣
** 日 期: 2004年5月02日
** 描 述: UART初始化
**-------------------------------------------------------------------------------------------------------
** 修改人:
** 日 期:
** 描 述:
**-------------------------------------------------------------------------------------------------------
*********************************************************************************************************
*/
UART_GLOBAL void UARTInit (eUARTNUM UARTNum);
/*
*********************************************************************************************************
** 函数名称: void UARTIntInit (eUARTNUM UARTNum)
** 全局变量: 无
** 作 者: 滕欣欣
** 日 期: 2004年5月02日
** 描 述: UART中断初始化
**-------------------------------------------------------------------------------------------------------
** 修改人:
** 日 期:
** 描 述:
**-------------------------------------------------------------------------------------------------------
*********************************************************************************************************
*/
UART_GLOBAL void UARTIntInit (eUARTNUM UARTNum);
/*
*********************************************************************************************************
** 函数名称: void UARTSend(eUARTNUM UARTNum,INT32U Len,INT8U *Buf)
** 全局变量: 无
** 作 者: 滕欣欣
** 日 期: 2004年5月02日
** 描 述: UART数据发送程序
**-------------------------------------------------------------------------------------------------------
** 修改人:
** 日 期:
** 描 述:
**-------------------------------------------------------------------------------------------------------
*********************************************************************************************************
*/
UART_GLOBAL void UARTSend(eUARTNUM UARTNum,INT32U Len,INT8U *Buf);
/*
************************************************************************************************************************
**函数原型 : void void UARTRcv(eUARTNUM UARTNum,INT32U Len,INT8U *Buf)
**参数说明 : Len -->> 接收字符长度;<=16;
Buf -->> 解收数据的缓冲区首址
**返回 值 : 无
**说 明 ： 本函数用于UART0接收数据,应用FIFO
************************************************************************************************************************
*/
UART_GLOBAL void UARTRcv(eUARTNUM UARTNum,INT32U Len,INT8U *Buf);
/*
*********************************************************************************************************
** 函数名称: void UARTxISR (void)
** 全局变量: 无
** 作 者: 滕欣欣
** 日 期: 2004年5月02日
** 描 述: UART中断服务程序
**-------------------------------------------------------------------------------------------------------
** 修改人:
** 日 期:
** 描 述:
**-------------------------------------------------------------------------------------------------------
*********************************************************************************************************
*/
UART_GLOBAL void __irq UART0ISR (void);
/*
**********************************************************************************************************
** End Of File
**********************************************************************************************************
*/
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