📄 initialization.c
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#include "system.h"
#include "ccblkfn.h"
#include "sysreg.h"
#include <sys\exception.h>
#include <cdefBF533.h>
void Init_PLL(void)
{
int iIMASK_Value;
sysreg_write(reg_SYSCFG, 0x32); //Initialize System Configuration Register
// set VCO/CCLK = 1, and VCO/SCLK = 5 (take effect immediately)
*pPLL_DIV = 0x0005;
// prepare PLL changes (set CLKIN/VCO = 22; takes effect after PLL programming sequence)
*pPLL_LOCKCNT = 0x0200; // time for PLL to stabilize
*pPLL_CTL = 0x2c00; // set VCO/CLKIN = 22
// execute PLL programming sequence
*pSIC_IWR = 0x00000001; // enable only PLL wakeup interrupt
iIMASK_Value = cli(); // disable interrupts
idle(); // wait for PLL wakeup interrupt
sti(iIMASK_Value);
}//end Init_PLL
void Init_UART(void)
{
UART_GCTL1 myUART_GCTL1;
UART_LCR1 myUART_LCR1;
myUART_GCTL1.Value = 0x00;
myUART_GCTL1.Bits.UCEN1 = 1;
*pUART_GCTL = myUART_GCTL1.Value; //*pUART_GCTL = 0x0001;
myUART_LCR1.Value = 0x00;
myUART_LCR1.Bits.WLS1 = 3;
myUART_LCR1.Bits.DLAB1= 1;
*pUART_LCR = myUART_LCR1.Value; // *pUART_LCR = 0x0083;
asm("ssync;");
*pUART_DLL = 0x0005; //0x2c0 = 704,0x305
*pUART_DLH = 0x0003; //UART Divisor Latch Registers
//CLKIN = 24.576MHz,VCO = 22*24.576MHz = 540.672MHz
//SCLK = 540.672/5 = 108.1344MHz
//divisor = 108.1344MHz/(16*9600)=704=0x2c0
asm("ssync;");
myUART_LCR1.Bits.DLAB1 = 0;
*pUART_LCR = myUART_LCR1.Value; // *pUART_LCR = 0x0003;
asm("ssync;");
*pUART_MCR = 0x0000; //Modem Control Register
//Loop=0(Loopback mode enable)
//Forces TX to high and disconnects RX from RSR
*pUART_IER = 0x0000; //UART Interrupt Enable Register
//ERBFI=1(Enable Receive Buffer Full Interrupt)
// 0:No interrupt
// 1:Generate RX interrupt if DR bit in UART_LSR is set
//ETBEI=0(Enable Transmit Buffer Empty Interrupt)
// 0:No interrrupt
// 1:Generate TX interrupt if THRE bit in UART_LSR is set
//ELSI=0(Enable RX Status Interrupt)
// 0:No interrupt
// 1:Generate line status interrupt if any of UART_LSR[4:1] is set
asm("ssync;");
}
void Init_SDRAM(void)
{
*pEBIU_SDRRC = 0x00000817; //SDRAM Refresh Rate Control Register
*pEBIU_SDBCTL = 0x00000001; //SDRAM Memory Bank Control Register
*pEBIU_SDGCTL = 0x0091998d; //SDRAM Memory Global Control Register
asm("ssync;");
}
void Init_EBIU(void)
{
*pEBIU_AMBCTL0 = 0x7bb07bb0;
*pEBIU_AMBCTL1 = 0x7bb07bb0;
*pEBIU_AMGCTL = 0x000f;
*pLight = 0xFF; // All lights off
*pLed = 0xFF;
}
void Init_Interrupts(void)
{
// assign core IDs to interrupts
*pSIC_IAR0 = 0xffffffff;
*pSIC_IAR1 = 0xf4ffffff; // UART -> ID4
*pSIC_IAR2 = 0xffffffff;
// assign ISRs to interrupt vectors
register_handler(ik_ivg11, UART_ISR); // UART ISR -> IVG 11
// enable Timer0 and FlagA interrupt
*pSIC_IMASK = 0x00004000;
}
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