sub4.rpt

用VHDL语言编写的两个四位二进制数相减

+ = Synchronous flipflop
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                 d:\工具\luoji\third\sub4\sub4.rpt
sub4

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC17 D0
        | +------------- LC23 D1
        | | +----------- LC22 D2
        | | | +--------- LC21 D3
        | | | | +------- LC20 |LPM_ADD_SUB:53|addcore:adder|addcore:adder0|gcp2
        | | | | | +----- LC19 |LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node1
        | | | | | | +--- LC18 |LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node2
        | | | | | | | +- LC24 |LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node3
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC17 -> - * * * - - - - | - * | <-- D0
LC20 -> - - - - - - - * | - * | <-- |LPM_ADD_SUB:53|addcore:adder|addcore:adder0|gcp2
LC19 -> - - * * - - - - | - * | <-- |LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node1
LC18 -> - - * * - - - - | - * | <-- |LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node2
LC24 -> - - - * - - - - | - * | <-- |LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node3

Pin
4    -> * * - - * * * - | - * | <-- A0
12   -> - * - - * * * - | - * | <-- A1
11   -> - - - - * - * - | - * | <-- A2
9    -> - - - - - - - * | - * | <-- A3
8    -> * * - - * * * - | - * | <-- B0
7    -> - * - - * * * - | - * | <-- B1
6    -> - - - - * - * - | - * | <-- B2
5    -> - - - - - - - * | - * | <-- B3


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                 d:\工具\luoji\third\sub4\sub4.rpt
sub4

** EQUATIONS **

A0       : INPUT;
A1       : INPUT;
A2       : INPUT;
A3       : INPUT;
B0       : INPUT;
B1       : INPUT;
B2       : INPUT;
B3       : INPUT;

-- Node name is 'D0' 
-- Equation name is 'D0', location is LC017, type is output.
D0       = _LC017~NOT;
_LC017~NOT = LCELL(!A0 $ !B0);

-- Node name is 'D1' 
-- Equation name is 'D1', location is LC023, type is output.
 D1      = LCELL( _EQ001 $ !D0);
  _EQ001 =  A0 &  A1 & !B0 & !B1
         #  A0 & !A1 & !B0 &  B1
         #  B0 &  _X001 &  _X002
         # !A0 &  _X001 &  _X002;
  _X001  = EXP( A1 & !B1);
  _X002  = EXP(!A1 &  B1);

-- Node name is 'D2' 
-- Equation name is 'D2', location is LC022, type is output.
 D2      = LCELL( _LC018 $  _EQ002);
  _EQ002 = !D0 &  _LC019;

-- Node name is 'D3' 
-- Equation name is 'D3', location is LC021, type is output.
 D3      = LCELL( _LC024 $  _EQ003);
  _EQ003 = !D0 &  _LC018 &  _LC019;

-- Node name is '|LPM_ADD_SUB:53|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC020', type is buried 
_LC020   = LCELL( _EQ004 $  GND);
  _EQ004 =  A0 & !B0 &  _X002 &  _X003
         #  A1 & !B1 &  _X003
         #  A2 & !B2;
  _X002  = EXP(!A1 &  B1);
  _X003  = EXP(!A2 &  B2);

-- Node name is '|LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node1' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC019', type is buried 
_LC019   = LCELL( _EQ005 $  GND);
  _EQ005 =  A0 &  A1 & !B0 & !B1
         #  A0 & !A1 & !B0 &  B1
         #  B0 &  _X001 &  _X002
         # !A0 &  _X001 &  _X002;
  _X001  = EXP( A1 & !B1);
  _X002  = EXP(!A1 &  B1);

-- Node name is '|LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC018', type is buried 
_LC018   = LCELL( _EQ006 $  _EQ007);
  _EQ006 =  A0 & !B0 &  _X002
         #  A1 & !B1;
  _X002  = EXP(!A1 &  B1);
  _EQ007 =  _X003 &  _X004;
  _X003  = EXP(!A2 &  B2);
  _X004  = EXP( A2 & !B2);

-- Node name is '|LPM_ADD_SUB:53|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC024', type is buried 
_LC024   = LCELL( _EQ008 $  _LC020);
  _EQ008 =  _X005 &  _X006;
  _X005  = EXP(!A3 &  B3);
  _X006  = EXP( A3 & !B3);



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                          d:\工具\luoji\third\sub4\sub4.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:01
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,477K