📄 and1.rpt
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| | +--------------------------- LC27 D4
| | | +------------------------- LC26 D5
| | | | +----------------------- LC30 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|gcp2
| | | | | +--------------------- LC17 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node2
| | | | | | +------------------- LC18 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node3
| | | | | | | +----------------- LC19 |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|~216~1
| | | | | | | | +--------------- LC20 |LPM_ADD_SUB:436|datab_node2
| | | | | | | | | +------------- LC21 |LPM_ADD_SUB:436|datab_node3
| | | | | | | | | | +----------- LC22 |LPM_ADD_SUB:436|datab_node4
| | | | | | | | | | | +--------- LC23 ~193~1
| | | | | | | | | | | | +------- LC24 ~202~1
| | | | | | | | | | | | | +----- LC25 ~291~1
| | | | | | | | | | | | | | +--- LC29 ~300~1
| | | | | | | | | | | | | | | +- LC31 ~309~1
| | | | | | | | | | | | | | | |
| | | | | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC30 -> - - - - - - * - - - - - - - - - | - * | <-- |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|gcp2
LC19 -> - - * * - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:430|addcore:adder|addcore:adder0|~216~1
LC22 -> - - * * - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:436|datab_node4
LC23 -> - - - * * * - * - - - - - - - - | - * | <-- ~193~1
LC24 -> - * - * * * - * - - - - - - - - | - * | <-- ~202~1
LC25 -> - - - * - - * * - - - - - - - - | - * | <-- ~291~1
LC29 -> - - - * * * - * - - - - - - - - | - * | <-- ~300~1
LC31 -> - * - * * * - * - - - - - - - - | - * | <-- ~309~1
Pin
4 -> * - - - - - - - * - - - - - - * | * * | <-- A0
6 -> - - - - - - - - - * - - * - * - | * * | <-- A1
7 -> - - * * - - - - - - * * - * - - | - * | <-- A2
8 -> * - - - - - - - - - - * * - - - | - * | <-- B0
9 -> - - - - - - - - - - - - - * * * | - * | <-- B1
5 -> - - * * - - - - * * * - - - - - | * * | <-- B2
LC1 -> - - * * - - - - - - - - - - - - | - * | <-- |LPM_ADD_SUB:436|addcore:adder|addcore:adder0|g4
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: d:\工具\luoji\third\and1\and1.rpt
and1
** EQUATIONS **
A0 : INPUT;
A1 : INPUT;
A2 : INPUT;
B0 : INPUT;
B1 : INPUT;
B2 : INPUT;
-- Node name is 'D0' = '~211~1'
-- Equation name is 'D0', location is LC028, type is output.
D0 = LCELL( _EQ001 $ GND);
_EQ001 = A0 & B0;
-- Node name is 'D1'
-- Equation name is 'D1', location is LC032, type is output.
D1 = LCELL( _EQ002 $ GND);
_EQ002 = _X001 & _X002;
_X001 = EXP( _LC024 & _LC031);
_X002 = EXP(!_LC024 & !_LC031);
-- Node name is 'D2'
-- Equation name is 'D2', location is LC008, type is output.
D2 = LCELL( _EQ003 $ GND);
_EQ003 = _X003 & _X004;
_X003 = EXP( A0 & B2 & _LC017);
_X004 = EXP(!_LC017 & !_LC020);
-- Node name is 'D3'
-- Equation name is 'D3', location is LC007, type is output.
D3 = LCELL( _EQ004 $ _EQ005);
_EQ004 = _X005 & _X006;
_X005 = EXP( A1 & B2 & _LC018);
_X006 = EXP(!_LC018 & !_LC021);
_EQ005 = A0 & B2 & _LC017;
-- Node name is 'D4'
-- Equation name is 'D4', location is LC027, type is output.
D4 = LCELL( _EQ006 $ _LC001);
_EQ006 = _X007 & _X008;
_X007 = EXP( A2 & B2 & _LC019);
_X008 = EXP(!_LC019 & !_LC022);
-- Node name is 'D5'
-- Equation name is 'D5', location is LC026, type is output.
D5 = LCELL( _EQ007 $ GND);
_EQ007 = A2 & B2 & _LC024 & _LC025 & _LC031 & _X009
# A2 & B2 & _LC023 & _LC025 & _LC029
# _LC001 & _X008;
_X009 = EXP(!_LC023 & !_LC029);
_X008 = EXP(!_LC019 & !_LC022);
-- Node name is '|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|gcp2' from file "addcore.tdf" line 160, column 8
-- Equation name is '_LC030', type is buried
_LC030 = LCELL( _EQ008 $ GND);
_EQ008 = _LC024 & _LC031 & _X009
# _LC023 & _LC029;
_X009 = EXP(!_LC023 & !_LC029);
-- Node name is '|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node2' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC017', type is buried
_LC017 = LCELL( _EQ009 $ _EQ010);
_EQ009 = _LC024 & _LC031;
_EQ010 = _X009 & _X010;
_X009 = EXP(!_LC023 & !_LC029);
_X010 = EXP( _LC023 & _LC029);
-- Node name is '|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|result_node3' from file "addcore.tdf" line 164, column 16
-- Equation name is '_LC018', type is buried
_LC018 = LCELL( _LC025 $ _LC030);
-- Node name is '|LPM_ADD_SUB:430|addcore:adder|addcore:adder0|~216~1' from file "addcore.tdf" line 350, column 16
-- Equation name is '_LC019', type is buried
-- synthesized logic cell
_LC019 = LCELL( _EQ011 $ GND);
_EQ011 = _LC024 & _LC025 & _LC031 & _X009
# _LC023 & _LC025 & _LC029;
_X009 = EXP(!_LC023 & !_LC029);
-- Node name is '|LPM_ADD_SUB:436|addcore:adder|addcore:adder0|g4' from file "addcore.tdf" line 158, column 5
-- Equation name is '_LC001', type is buried
_LC001 = LCELL( _EQ012 $ _EQ013);
_EQ012 = A0 & B2 & _LC017 & _X005 & _X006;
_X005 = EXP( A1 & B2 & _LC018);
_X006 = EXP(!_LC018 & !_LC021);
_EQ013 = A1 & B2 & _LC018;
-- Node name is '|LPM_ADD_SUB:436|datab_node2' from file "lpm_add_sub.tdf" line 114, column 14
-- Equation name is '_LC020', type is buried
_LC020 = LCELL( _EQ014 $ GND);
_EQ014 = A0 & B2;
-- Node name is '|LPM_ADD_SUB:436|datab_node3' from file "lpm_add_sub.tdf" line 114, column 14
-- Equation name is '_LC021', type is buried
_LC021 = LCELL( _EQ015 $ GND);
_EQ015 = A1 & B2;
-- Node name is '|LPM_ADD_SUB:436|datab_node4' from file "lpm_add_sub.tdf" line 114, column 14
-- Equation name is '_LC022', type is buried
_LC022 = LCELL( _EQ016 $ GND);
_EQ016 = A2 & B2;
-- Node name is '~193~1'
-- Equation name is '~193~1', location is LC023, type is buried.
-- synthesized logic cell
_LC023 = LCELL( _EQ017 $ GND);
_EQ017 = A2 & B0;
-- Node name is '~202~1'
-- Equation name is '~202~1', location is LC024, type is buried.
-- synthesized logic cell
_LC024 = LCELL( _EQ018 $ GND);
_EQ018 = A1 & B0;
-- Node name is '~291~1'
-- Equation name is '~291~1', location is LC025, type is buried.
-- synthesized logic cell
_LC025 = LCELL( _EQ019 $ GND);
_EQ019 = A2 & B1;
-- Node name is '~300~1'
-- Equation name is '~300~1', location is LC029, type is buried.
-- synthesized logic cell
_LC029 = LCELL( _EQ020 $ GND);
_EQ020 = A1 & B1;
-- Node name is '~309~1'
-- Equation name is '~309~1', location is LC031, type is buried.
-- synthesized logic cell
_LC031 = LCELL( _EQ021 $ GND);
_EQ021 = A0 & B1;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information d:\工具\luoji\third\and1\and1.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:01
Timing SNF Extractor 00:00:00
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 3,864K
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