mcbsp_recv_slave.c

关于TI公司的DSP开发的宝贵资料,主要涉及TI C6000系列DSP器件的MCBSP部分的信息(包括硬件、软件)

/*---------------------------------------------------------------------------------*/
/*  mcbsp_recv_slave.c V1.00                                                       */
/*  Copyright (c) 2001 Texas Instruments Incorporated                              */
/*---------------------------------------------------------------------------------*/
/*

    6/26/01
	Written by: Vassos S. Soteriou
	
   mcbsp_recv_slave.c:
   This program sets the McBSP0 of the TMS320C6000 devices in the data receive mode,
   to receive data from the McBSP of another C6000 device.  This program supports all
   the Texas Instruments TMS320C6000 DSPs, those that use the DMA controller or the
   Enhanced DMA controller (EDMA). For those that use the DMA controller, DMA channel
   1 services the McBSP for data receive. The vecs.asm assembly code file is used to
   hookup the c_int09() ISR to the corresponding interrupt.  Channel 1 is hooked up
   to interrupt 09 for data receive, the DMA controller has individual interrupts
   for each DMA channel.  The EDMA controller, however, generates a single interrupt
   to the CPU (EDMA_INT) on behalf of all 16 channels (C621x/C671x) or 64 channels
   (C64x). The various control registers and bit fields facilitate EDMA interrupt
   generation.  CPU_INT8 is responsible for all the EDMA channels. The sample code
   is based on TI's CSL 2.0. Please refer to the TMS320C6000 Chip Support Library API
   User's Guide for further information.     
   Note that any DMA channel with any interrupt and any McBSP can be used for this 
   transfer, this is just sample code that can be used as a reference.
*/  
/* Chip definition, change this accordingly */
#define CHIP_6202 1

/* Include files */
#include <c6x.h>
#include <csl.h>         /* CSL library   */
#include <csl_dma.h>     /* DMA_SUPPORT   */
#include <csl_edma.h>    /* EDMA_SUPPORT  */
#include <csl_irq.h>     /* IRQ_SUPPORT   */
#include <csl_mcbsp.h>   /* MCBSP_SUPPORT */

/*--------------------------------------------------------------------------------*/
/* Define constants */
#define FALSE 0
#define TRUE 1

#define DMA_XFER 8
#define XFER_TYPE DMA_XFER
#define BUFFER_SIZE 256  /* set same value as xmit */
#define ELEMENT_COUNT 32 /* set element_count=<buffer_size, set same value as xmit*/

/* Global variables used in interrupt ISRs */
volatile int recv0_done = FALSE;
/*--------------------------------------------------------------------------------*/
/* Declare CSL objects */
MCBSP_Handle hMcbsp0;       /* Handles for McBSP */

#if (DMA_SUPPORT)
DMA_Handle hDma1;           /* Handle for DMA    */
#endif

#if (EDMA_SUPPORT)          /* Handles for EDMA  */
EDMA_Handle hEdma1;
EDMA_Handle hEdmadummy;
#endif
/*--------------------------------------------------------------------------------*/
/* External functions and function prototypes */

void init_mcbsp0_slave(void);   /* Function prototypes */
void set_interrupts_dma(void);
void set_interrupts_edma(void);

/* Include the vector table to call the IRQ ISRs hookup */
extern far void vectors();

/*--------------------------------------------------------------------------------*/
/* main()                                                                         */
/*--------------------------------------------------------------------------------*/

void main(void)
{

/* Declaration of local variables */
static int element_count, xfer_type;

static Uint32 dmaInbuff[BUFFER_SIZE];  /* buffer for DMA supporting devices  */
static Uint32 edmaInbuff[BUFFER_SIZE]; /* buffer for EDMA supporting devices */

IRQ_setVecs(vectors); /* point to the IRQ vector table */

element_count = ELEMENT_COUNT;
xfer_type = XFER_TYPE;

/* initialize the CSL library */
CSL_init();

init_mcbsp0_slave();

/* Enable sample rate generator GRST=1 */
MCBSP_enableSrgr(hMcbsp0);       /* Handle to SRGR */

switch (xfer_type) {
case DMA_XFER:

  #if (DMA_SUPPORT)       /* for DMA supporting devices */
  DMA_reset(INV);         /* reset all DMA channels */
  #endif

  #if (EDMA_SUPPORT)           /* for EDMA supporting devices */
  EDMA_clearPram(0x00000000);  /* Clear PaRAM RAM of the EDMA */
  set_interrupts_edma();
  #endif

/*--------------------------------------------------------------------------------*/
/* DMA channel 1 config structure                                                 */
/*--------------------------------------------------------------------------------*/

#if (DMA_SUPPORT)       /* for DMA supporting devices */   
  /* Channel 1 receives the data */
  hDma1 = DMA_open(DMA_CHA1, DMA_OPEN_RESET);  /* Handle to DMA channel 1 */
    DMA_configArgs(hDma1,
       DMA_PRICTL_RMK(
           DMA_PRICTL_DSTRLD_DEFAULT,
           DMA_PRICTL_SRCRLD_DEFAULT,
           DMA_PRICTL_EMOD_DEFAULT,
           DMA_PRICTL_FS_DEFAULT,
           DMA_PRICTL_TCINT_ENABLE, /* TCINT =1                              */
           DMA_PRICTL_PRI_DMA,      /* DMA high priority                     */
           DMA_PRICTL_WSYNC_REVT0,  /* Set synchronization event REVT0=01101 */
           DMA_PRICTL_RSYNC_DEFAULT,
           DMA_PRICTL_INDEX_DEFAULT,
           DMA_PRICTL_CNTRLD_DEFAULT,
           DMA_PRICTL_SPLIT_DEFAULT,
           DMA_PRICTL_ESIZE_32BIT,  /* Element size 32 bits                  */
           DMA_PRICTL_DSTDIR_DEFAULT,
           DMA_PRICTL_SRCDIR_INC,   /* Increment source by element size      */
           DMA_PRICTL_START_DEFAULT
           ),
        DMA_SECCTL_RMK(
           DMA_SECCTL_WSPOL_NA,    /* only available for 6202 and 6203 devices */
           DMA_SECCTL_RSPOL_NA,    /* only available for 6202 and 6203 devices */
           DMA_SECCTL_FSIG_NA,     /* only available for 6202 and 6203 devices */
           DMA_SECCTL_DMACEN_DEFAULT,
           DMA_SECCTL_WSYNCCLR_DEFAULT,
           DMA_SECCTL_WSYNCSTAT_DEFAULT,
           DMA_SECCTL_RSYNCCLR_DEFAULT,
           DMA_SECCTL_RSYNCSTAT_DEFAULT,
           DMA_SECCTL_WDROPIE_DEFAULT,
           DMA_SECCTL_WDROPCOND_DEFAULT,
           DMA_SECCTL_RDROPIE_DEFAULT,
           DMA_SECCTL_RDROPCOND_DEFAULT,
           DMA_SECCTL_BLOCKIE_ENABLE, /* BLOCK IE=1 enables DMA channel int    */
           DMA_SECCTL_BLOCKCOND_DEFAULT,
           DMA_SECCTL_LASTIE_DEFAULT,
           DMA_SECCTL_LASTCOND_DEFAULT,
           DMA_SECCTL_FRAMEIE_DEFAULT,
           DMA_SECCTL_FRAMECOND_DEFAULT,
           DMA_SECCTL_SXIE_DEFAULT,
           DMA_SECCTL_SXCOND_DEFAULT
           ),
        DMA_SRC_RMK(MCBSP_ADDRH(hMcbsp0, DRR)),
        DMA_DST_RMK((Uint32)dmaInbuff),
        DMA_XFRCNT_RMK(
           DMA_XFRCNT_FRMCNT_DEFAULT,
           DMA_XFRCNT_ELECNT_OF(element_count)  /* set recv element count */
           )
); 

set_interrupts_dma(); /* initialize the interrupt(s)                                  */
                      /* enable the interrupt after the DMA channels are opened as    */
                      /* the DMA_OPEN_RESET clears and disables the channel interrupt */
                      /* once specified and clears the corresponding interrupt bits   */
                      /* in the IER. This is not applicable for the EDMA channel open */
                      /* case                                                         */ 
DMA_start(hDma1);     /* Start DMA channel 1 */

#endif  /* end for dma supporting devices */

/*--------------------------------------------------------------------------------*/
/* EDMA channel 13 config structure                                               */
/*--------------------------------------------------------------------------------*/

  #if (EDMA_SUPPORT)      /* for EDMA supporting devices  */  
     
hEdma1 = EDMA_open(EDMA_CHA_REVT0, EDMA_OPEN_RESET);
EDMA_configArgs(hEdma1,

#if (!C64_SUPPORT)
     EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,       /* High priority EDMA */
        EDMA_OPT_ESIZE_32BIT,    /* Element size 32 bits */
        EDMA_OPT_2DS_DEFAULT,
        EDMA_OPT_SUM_DEFAULT,
        EDMA_OPT_2DD_DEFAULT,
        EDMA_OPT_DUM_INC,        /* Destination increment by element size */
        EDMA_OPT_TCINT_YES,      /* Enable Transfer Complete Interrupt    */
        EDMA_OPT_TCC_OF(13),     /* TCCINT = 0xD, REVT0                   */
        EDMA_OPT_LINK_YES,       /* Enable linking to NULL table          */
        EDMA_OPT_FS_NO
        ),
#endif

#if (C64_SUPPORT)
     EDMA_OPT_RMK(
        EDMA_OPT_PRI_HIGH,       /* High priority EDMA */
        EDMA_OPT_ESIZE_32BIT,    /* Element size 32 bits */
        EDMA_OPT_2DS_DEFAULT,
        EDMA_OPT_SUM_DEFAULT,
        EDMA_OPT_2DD_DEFAULT,
        EDMA_OPT_DUM_INC,        /* Destination increment by element size */
        EDMA_OPT_TCINT_YES,      /* Enable Transfer Complete Interrupt    */
        EDMA_OPT_TCC_OF(13),     /* TCCINT = 0xD, REVT0                   */
        EDMA_OPT_TCCM_DEFAULT,
        EDMA_OPT_ATCINT_DEFAULT,
        EDMA_OPT_ATCC_DEFAULT,
        EDMA_OPT_PDTS_DEFAULT,
        EDMA_OPT_PDTD_DEFAULT,
		EDMA_OPT_LINK_YES,       /* Enable linking to NULL table          */
        EDMA_OPT_FS_NO
        ),
#endif
        EDMA_SRC_RMK(MCBSP_ADDRH(hMcbsp0, DRR)), /* recv addr to edmaInbuff */
        EDMA_CNT_RMK(0, element_count), /* set count equal to element_count */
        EDMA_DST_RMK((Uint32)edmaInbuff), /* dst to DRR0                    */
        EDMA_IDX_RMK(0,0),
        EDMA_RLD_RMK(0,0)
        );

  hEdmadummy = EDMA_allocTable(-1); /* Dynamically allocates PaRAM RAM table */
  EDMA_configArgs(hEdmadummy, /* Dummy or Terminating Table in PaRAM         */
         0x00000000,          /* Terminate EDMA transfers by linking to      */     
         0x00000000,          /* this NULL table                             */
         0x00000000,         
         0x00000000,  
         0x00000000,        
         0x00000000
         );

  EDMA_link(hEdma1, hEdmadummy); /* Link terminating event to the EDMA event */

  EDMA_enableChannel(hEdma1);    /* Enable EDMA channel */

  #endif  /* end for EDMA supporting devices */  
} 

/* Enable McBSP channel */
MCBSP_enableRcv(hMcbsp0); /* McBSP port 0 as the transmitter         */

/* To flag an interrupt to the CPU when DMA transfer/receive is done */
#if (DMA_SUPPORT)
  while (!recv0_done);
#endif