📄 logicl-schematic1-logic.out
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**** 04/25/08 20:10:32 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-logic" [ D:\Monday24\Logicl\logicl-schematic1-logic.sim ]
**** CIRCUIT DESCRIPTION
******************************************************************************
** Creating circuit file "logicl-schematic1-logic.sim.cir"
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS
*Libraries:
* Local Libraries :
.STMLIB ".\LOGICL.stl"
* From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:
.lib "nom.lib"
*Analysis directives:
.TRAN 0 32us 0 0.1u
.PROBE V(*) I(*) W(*) D(*) NOISE(*)
.INC ".\logicl-SCHEMATIC1.net"
**** INCLUDING logicl-SCHEMATIC1.net ****
* source LOGICL
X_U5A S0 N01756 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM1 FSTIM(2) $G_DPWR $G_DGND S1 S0 IO_STM FILE="sig.stm" IO_LEVEL=0
+ SIGNAMES=s1 s0
X_U6A N01563 N01717 N01756 Y0 $G_DPWR $G_DGND 7411 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U7A N01717 N01563 S0 Y1 $G_DPWR $G_DGND 7411 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM2 STIM(1,1) $G_DPWR $G_DGND A IO_STM IO_LEVEL=0
+ 0 0
+ +.5uS 1
+REPEAT FOREVER
+ +.5uS 0
+ +.5uS 1
+ ENDREPEAT
X_U8A N01563 S1 N01756 Y2 $G_DPWR $G_DGND 7411 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U9A S1 N01563 S0 Y3 $G_DPWR $G_DGND 7411 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2A A N01497 N01563 $G_DPWR $G_DGND 7408 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U3A E N01497 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM3 STIM(1,0) $G_DPWR $G_DGND E IO_STM STIMULUS=E
X_U4A S1 N01717 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
**** RESUMING logicl-schematic1-logic.sim.cir ****
.END
* F:\LOGICL\LOGICL.stl written on Fri Apr 25 15:08:00 2008
* by Stimulus Editor -- Serial Number: 1 -- Version 9.2
;!Stimulus Get
;! E Digital
;!Ok
;!Plot Axis_Settings
;!Xrange 0s 32us
;!AutoUniverse
;!XminRes 1ns
;!YminRes 1n
;!Ok
.STIMULUS E STIM (1, 1) ;! CLOCKP 8us 4us 0 0
+ +0s 0
+ +4us 1
+ Repeat Forever
+ +4us 0
+ +4us 1
+ EndRepeat
**** 04/25/08 20:10:32 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-logic" [ D:\Monday24\Logicl\logicl-schematic1-logic.sim ]
**** Digital Gate MODEL PARAMETERS
******************************************************************************
D_04 D_11 D_08
TPLHMN 4.800000E-09 6.750001E-09 7.000000E-09
TPLHTY 12.000000E-09 16.875000E-09 17.500000E-09
TPLHMX 22.000000E-09 27.000000E-09 27.000000E-09
TPHLMN 3.200000E-09 4.750000E-09 4.800000E-09
TPHLTY 8.000000E-09 11.875000E-09 12.000000E-09
TPHLMX 15.000000E-09 19.000000E-09 19.000000E-09
**** 04/25/08 20:10:32 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********
** Profile: "SCHEMATIC1-logic" [ D:\Monday24\Logicl\logicl-schematic1-logic.sim ]
**** Digital IO MODEL PARAMETERS
******************************************************************************
IO_STM IO_STD
DRVL 0 104
DRVH 0 96.4
AtoD1 AtoD_STD
AtoD2 AtoD_STD_NX
AtoD3 AtoD_STD
AtoD4 AtoD_STD_NX
DtoA1 DtoA_STM DtoA_STD
DtoA2 DtoA_STM DtoA_STD
DtoA3 DtoA_STM DtoA_STD
DtoA4 DtoA_STM DtoA_STD
TSWHL1 1.511000E-09
TSWHL2 1.487000E-09
TSWHL3 1.511000E-09
TSWHL4 1.487000E-09
TSWLH1 3.517000E-09
TSWLH2 3.564000E-09
TSWLH3 3.517000E-09
TSWLH4 3.564000E-09
TPWRT 100.000000E+03 100.000000E+03
JOB CONCLUDED
TOTAL JOB TIME .09
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