logicl-schematic1-logic.out.1

个学期下来的电子CAD课程实验

**** 04/25/08 15:09:15 ********* PSpice 9.2 (Mar 2000) ******** ID# 1 ********

 ** Profile: "SCHEMATIC1-logic"  [ F:\Logicl\logicl-SCHEMATIC1-logic.sim ] 


 ****     CIRCUIT DESCRIPTION


******************************************************************************




** Creating circuit file "logicl-SCHEMATIC1-logic.sim.cir" 
** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

*Libraries: 
* Local Libraries :
.STMLIB ".\LOGICL.stl" 
* From [PSPICE NETLIST] section of C:\Program Files\Orcad\PSpice\PSpice.ini file:
.lib "nom.lib" 

*Analysis directives: 
.TRAN  0 32us 0 0.1u 
.PROBE V(*) I(*) W(*) D(*) NOISE(*) 
.INC ".\logicl-SCHEMATIC1.net" 



**** INCLUDING logicl-SCHEMATIC1.net ****
* source LOGICL
X_U5A         S0 N01756 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM1         FSTIM(2) $G_DPWR $G_DGND M_UN0001 M_UN0002 IO_STM
+  FILE="sig.stm" IO_LEVEL=0 SIGNAMES=s1 s0
X_U6A         N01563 N01717 N01756 Y0 $G_DPWR $G_DGND 7411 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U7A         N01717 N01563 S0 Y1 $G_DPWR $G_DGND 7411 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM2         STIM(1,1) $G_DPWR $G_DGND A IO_STM IO_LEVEL=0 
+ 0 0
+ +.5uS 1
+REPEAT FOREVER
+ +.5uS 0
+  +.5uS 1
+ ENDREPEAT
X_U8A         N01563 S1 N01756 Y2 $G_DPWR $G_DGND 7411 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U9A         S1 N01563 S0 Y3 $G_DPWR $G_DGND 7411 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U2A         A N01497 N01563 $G_DPWR $G_DGND 7408 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
X_U3A         E N01497 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0
U_DSTM3         STIM(1,0) $G_DPWR $G_DGND E IO_STM STIMULUS=E
X_U4A         S1 N01717 $G_DPWR $G_DGND 7404 PARAMS:
+ IO_LEVEL=0 MNTYMXDLY=0

**** RESUMING logicl-SCHEMATIC1-logic.sim.cir ****
.END

I/O ERROR -- Unable to open stimulus file "sig.stm".