clcd.c

ARM9基于WINDOWSCE的BSP源代码

/*
*
*
* THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
* ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
* PARTICULAR PURPOSE.
*
* Copyright (c) 1995-1998  Microsoft Corporation
*
* Release Status:OS005-SW-70002-r0p0-00REL0
* $Copyright: 
* ----------------------------------------------------------------
* This confidential and proprietary software may be used only as
* authorised by a licensing agreement from ARM Limited
*   (C) COPYRIGHT 2004 ARM Limited
*       ALL RIGHTS RESERVED
* The entire notice above must be reproduced on all authorised
* copies and copies may only be made to the extent permitted
* by a licensing agreement from ARM Limited.
* ----------------------------------------------------------------
* File:     clcd.c,v
* Revision: 1.3
* ----------------------------------------------------------------
* $  
* Module Name:  
*  clcd.c
*
* Abstract:  
*    CLCD & panel hardware specific configuration functions 
*
*
--*/

/*

  revised by ww for 240X320 (Nov,24,2004)

*/
#include <windows.h>
#include <types.h>
#include "DispDrvr.h"
#include "board.h"
#include "palette.h"
#include <platform.h>
#include <ceddk.h>


// Watermark info
const PTCHAR part_name = { TEXT("Windows CE .NET PL110 Colour LCD Support Code") };
const PTCHAR part_num = { TEXT("OS005-SW-70002-r0p0-00REL0") };

#ifdef VGA
// Following are set of parameters for SHARP 8.4 TFT panel, adjust them for 
// other panel
#define     DISPDRVR_CXSCREEN  640  // LCD Panel physical size - width
#define     DISPDRVR_CYSCREEN  480  // LCD Panel physical size - height
/*time 0-time2*/
#define TIM0_VALUE 0x7810409c
#define TIM1_VALUE 0x10010ddf
#define TIM2_VALUE 0x027f3800
#else		//QVGA
// Following are set of parameters for SHARP 8.4 TFT panel, adjust them for 
// other panel
#define     DISPDRVR_CXSCREEN  240  // LCD Panel physical size - width
#define     DISPDRVR_CYSCREEN  320  // LCD Panel physical size - height
/*time 0-time2*/
#define TIM0_VALUE 0x010E0C38
#define TIM1_VALUE 0x00061D3F
#define TIM2_VALUE 0x00ef0006
#endif

int DispDrvr_cxScreen = DISPDRVR_CXSCREEN;
int DispDrvr_cyScreen = DISPDRVR_CYSCREEN;

/* Sync and porch parameters (some determined empirically) */
#define ACBIAS          0   
#define FRAME_RATE      100
#define LCD_CLOCK       (25 * 1000000)

// Versatile settings for VGA and LCD output settings for 320 x 240
#define VSYNC_VALUE     8 // (Minus one in later setting)
#define VFRONT_VALUE    7//11
#define HSYNC_VALUE     10//64  // (Minus one in later setting)
#define HFRONT_VALUE    10 // 32  // (Minus one in later setting)
#define HBACK_VALUE     10//64  // (Minus one in later setting)


// Best quality output for CLCD display
#define VBACK_VALUE    7// 9
#define DATADRIVE       0  //IPC

#define VSYNCACTIVE     1 //IVS
#define HSYNCACTIVE     1//IHS
#define CLOCKSOURCE     0//CLKSEL
#define TFTCLAC         1  //IEO
#define CLLEDELAY       0 //LED line-end delay
#define PCD_VALUE       4

// End of parameters for SHARP 8.4 TFT panel

//  Frame buffer location
#define CLCD_FRAME_BUFFER   PHYS_CLCD_BUFF_BASE

// Some global variables
int DispDrvr_cdwStride;
void * DispDrvrPhysicalFrameBuffer = (void *)(VA_CLCD_BUFF_BASE);

typedef unsigned char * P_BYTE;

/* 
This access pair is declared as a byte pointer to allow the 
byte calculated register offsets to be applied.

The actual access function will cast these to volatile to 
force the data to always be current.
  */

P_BYTE v_pDisplayRegs = NULL;
P_BYTE v_pSYS_CTRLRegisters = NULL;
    
ULONG Cntrl;
// End of Some global variables

// Macros for Timing register
/* Bit operation */
#define apBIT_MASK(__bws) ((ULONG)(((bw ## __bws)==32)?0xFFFFFFFF:\
        ((1U << (bw ## __bws)) - 1)) << (bs ## __bws))

#define apBIT_SET(__datum, __bws, __val) ((__datum) = ((ULONG) \
        (__datum) & (ULONG)~(apBIT_MASK(__bws))) | \
        ((ULONG) ((ULONG)(__val) << (ULONG)(bs ## __bws)) & \
        (apBIT_MASK(__bws))))

/*********** Timing 0 register bitfields ****************/
#define bwCLCD_TIMING0_PPL    6
#define bsCLCD_TIMING0_PPL    2
#define CLCD_TIMING0_MASK_PPL    apBIT_MASK(CLCD_TIMING0_PPL)

/* Horiz. sync pulse width */
#define bwCLCD_TIMING0_HSW    8
#define bsCLCD_TIMING0_HSW    8
#define CLCD_TIMING0_MASK_HSW    apBIT_MASK(CLCD_TIMING0_HSW)

/* Horiz. front porch */
#define bwCLCD_TIMING0_HFP    8
#define bsCLCD_TIMING0_HFP    16
#define CLCD_TIMING0_MASK_HFP    apBIT_MASK(CLCD_TIMING0_HFP)

/* Horiz. back porch */
#define bwCLCD_TIMING0_HBP    8
#define bsCLCD_TIMING0_HBP    24
#define CLCD_TIMING0_MASK_HBP    apBIT_MASK(CLCD_TIMING0_HBP)

/*********** Timing 1 register bitfields ****************/
/* Lines per screen */
#define bwCLCD_TIMING1_LPP    10
#define bsCLCD_TIMING1_LPP    0
#define CLCD_TIMING1_MASK_LPP    apBIT_MASK(CLCD_TIMING1_LPP)

/* Vertical sync pulse width */
#define bwCLCD_TIMING1_VSW    6
#define bsCLCD_TIMING1_VSW    10
#define CLCD_TIMING1_MASK_VSW    apBIT_MASK(CLCD_TIMING1_VSW)

/* Vertical front porch */
#define bwCLCD_TIMING1_VFP    8
#define bsCLCD_TIMING1_VFP    16
#define CLCD_TIMING1_MASK_VFP    apBIT_MASK(CLCD_TIMING1_VFP)

/* Vertical back porch */
#define bwCLCD_TIMING1_VBP    8
#define bsCLCD_TIMING1_VBP    24
#define CLCD_TIMING1_MASK_VBP    apBIT_MASK(CLCD_TIMING1_VBP)

/*********** Timing 2 register bitfields ****************/
/* Panel clock divisor */
#define bwCLCD_TIMING2_PCD    5
#define bsCLCD_TIMING2_PCD    0
#define CLCD_TIMING2_MASK_PCD    apBIT_MASK(CLCD_TIMING2_PCD)

/* Clock selector */
#define bwCLCD_TIMING2_CLKSEL 1
#define bsCLCD_TIMING2_CLKSEL 5
#define CLCD_TIMING2_MASK_CLKSEL apBIT_MASK(CLCD_TIMING2_CLKSEL)

/* AC bias pin frequency */
#define bwCLCD_TIMING2_ACB    5
#define bsCLCD_TIMING2_ACB    6
#define CLCD_TIMING2_MASK_ACB    apBIT_MASK(CLCD_TIMING2_ACB)

/* Invert Vsync */
#define bwCLCD_TIMING2_IVS    1
#define bsCLCD_TIMING2_IVS    11
#define CLCD_TIMING2_MASK_IVS    apBIT_MASK(CLCD_TIMING2_IVS)

/* Interc Hsync */
#define bwCLCD_TIMING2_IHS    1
#define bsCLCD_TIMING2_IHS    12
#define CLCD_TIMING2_MASK_IHS    apBIT_MASK(CLCD_TIMING2_IHS)

/* Invert Panel Clock */
#define bwCLCD_TIMING2_IPC    1
#define bsCLCD_TIMING2_IPC    13
#define CLCD_TIMING2_MASK_IPC    apBIT_MASK(CLCD_TIMING2_IPC)

/* Invert Output Enable */
#define bwCLCD_TIMING2_IEO    1
#define bsCLCD_TIMING2_IEO    14
#define CLCD_TIMING2_MASK_IEO    apBIT_MASK(CLCD_TIMING2_IEO)

/* Clocks per line */
#define bwCLCD_TIMING2_CPL    10
#define bsCLCD_TIMING2_CPL    16
#define CLCD_TIMING2_MASK_CPL    apBIT_MASK(CLCD_TIMING2_CPL)

/* Bypass panel clock divider */
#define bwCLCD_TIMING2_BCD    1
#define bsCLCD_TIMING2_BCD    26
#define CLCD_TIMING2_MASK_BCD    apBIT_MASK(CLCD_TIMING2_BCD)

/*********** Timing 3 register bitfields ****************/
/* Frame end delay */
#define bwCLCD_TIMING3_LED    7
#define bsCLCD_TIMING3_LED    0
#define CLCD_TIMING3_MASK_LED    apBIT_MASK(CLCD_TIMING3_LED)

/* Frame end enable */
#define bwCLCD_TIMING3_LEE    1
#define bsCLCD_TIMING3_LEE    16
#define CLCD_TIMING3_MASK_LEE    apBIT_MASK(CLCD_TIMING3_LEE)
// End of Macros for Timing register

// CLCD register offset
#define LCD_TIMING0_OFFSET      0x00
#define LCD_TIMING1_OFFSET      0x04
#define LCD_TIMING2_OFFSET      0x08
#define LCD_TIMING3_OFFSET      0x0C

// Versatile's LCD controller has the control register at offset 0x18
#define LCD_CONTROL_OFFSET      0x1c

#define LCD_FRAMBUF_OFFSET      0x10
#define LCD_PALETTE_OFFSET      0x200

// Versatile's LCD mode control settings
#define ARMVPB_LCD_MODE_MASK  0x3     // mask for the LCD Mux mode

#define ARMVPB_888_MODE          0x0     // bits 1:0 = 0b000 for 24 bit 8:8:8 mode
#define ARMVPB_555_MODE          0x1     // bits 1:0 = 0b001 for 16 bit 1:5:5:5 mode
#define ARMVPB_565_MODE_R_LSB    0x2     // bits 1:0 = 0b010 for 16 bit 5:6:5 mode
#define ARMVPB_565_MODE_B_LSB    0x3     // bits 1:0 = 0b010 for 16 bit 5:6:5 mode

// Bit positions within the control register
#define LCD_CONTROL_PWR         0x0001  /* bit 0 */
#define LCD_CONTROL_1BPP        0x0000  /* bits 1-3 */
#define LCD_CONTROL_2BPP        0x0002
#define LCD_CONTROL_4BPP        0x0004
#define LCD_CONTROL_8BPP        0x0006
#define LCD_CONTROL_16BPP       0x0008
#define LCD_CONTROL_24BPP       0x000A
#define LCD_CONTROL_BW          0x0010  /* bit 4 */
#define LCD_CONTROL_TFT         0x0020  /* bit 5 */
#define LCD_CONTROL_MONO8       0x0040  /* bit 6 */
#define LCD_CONTROL_DUAL        0x0080  /* bit 7 */
#define LCD_CONTROL_BGR         0x0100  /* bit 8 */
#define LCD_CONTROL_BEBO        0x0200  /* bit 9: Big-endian byte order */
#define LCD_CONTROL_BEPO        0x0400  /* bit 10: Big-endian pixel order */
#define LCD_CONTROL_ENABLE      0x0800  /* bit 11 */
#define LCD_CONTROL_VCOMP_BACKP 0x1000  /* bits 12-13 */
#define LCD_CONTROL_MASK_PWR            0x0001  /* bit 0 */
#define LCD_CONTROL_MASK_ENABLE         0x0800  /* bit 11 */

// Mapped space
#define SIZE_CLCD_CNTL_REGS     0x800
#define SIZE_SYS_CNTL_REGS      0x80

// Bit operation macro for regsters
#define READ_REGISTER_ULONG(reg) \
           (*(volatile unsigned long * const)(reg))
#define WRITE_REGISTER_ULONG(reg, val) \
           (*(volatile unsigned long * const)(reg)) = (val)
#define READ_REGISTER_USHORT(reg) \
           (*(volatile unsigned short * const)(reg))
#define WRITE_REGISTER_USHORT(reg, val) \
           (*(volatile unsigned short * const)(reg)) = (val)
#define READ_REGISTER_UCHAR(reg) \
           (*(volatile unsigned char * const)(reg))
#define WRITE_REGISTER_UCHAR(reg, val) \
           (*(volatile unsigned char * const)(reg)) = (val)

// Locally used functions declration
static void DispPowerOn(BOOL bInPowerHandler);
static void DispPowerOff(BOOL bInPowerHandler);

// Convert 24bit RGB into 16bit value to fit into CLCD palette register
#ifndef CLCD_565    // in original 1555 mode

//I|BBBBB|GGGGG|RRRRR
//(1)  >>3   red lsb
//(2)  >>3 then <<5 so <<2 
//(3)  >>3 then <<10 so <<7  
#define PALCONV(_v_) (((((UINT32)(_v_).peRed  ) >> 3) & 0x001f) | \
                      ((((UINT32)(_v_).peGreen) << 2) & 0x03e0) | \
                      ((((UINT32)(_v_).peBlue ) << 7) & 0x7c00))

#else                   // new 565 true 16 bit mapping

//RRRRR|GGGGGG|BBBBB
//(1) >>3 then <<11 so <<8
//(2) >>2 then <<5  so <<3
//(3) >>3 
#define PALCONV(_v_) (((((UINT32)(_v_).peRed  ) << 8) & 0xF800) | \
                      ((((UINT32)(_v_).peGreen) << 3) & 0x07e0) | \
                      ((((UINT32)(_v_).peBlue ) >> 3) & 0x001f))

#endif

/******************************************************************************\
* Description:  Find the required ratio of the Panel Clock to the CLCD clock.  *
* Operation:    The Panel Clock is generated by a divisor applied to the CLCD  *
*               Clock. This function uses values from the parameter structure  *