📄 sci.h
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/*
** Release Status:OS005-SW-70002-r0p0-00REL0
** $Copyright:
** ----------------------------------------------------------------
** This confidential and proprietary software may be used only as
** authorised by a licensing agreement from ARM Limited
** (C) COPYRIGHT 2004 ARM Limited
** ALL RIGHTS RESERVED
** The entire notice above must be reproduced on all authorised
** copies and copies may only be made to the extent permitted
** by a licensing agreement from ARM Limited.
** ----------------------------------------------------------------
** File: Sci.h,v
** Revision: 1.1
** ----------------------------------------------------------------
** $
*/
//const unsigned long SCI0_BASE = 0x101F0000; //PHYS_SC0_BASE;
// Size of the SCI0 hardware register space
#define SCI0_HWREGS_SIZE 0x1000
#define SMCLIB_CE 1
#ifndef PSMARTCARD_EXTENSION
#include "smclib.h"
#endif
typedef volatile struct PL131_xReg
{
DWORD RegData; /* SCIDATA - Data register*/
DWORD RegCtrl0; /* SCICR0 - Control register 0*/
DWORD RegCtrl1; /* SCICR1 - Control register 1*/
DWORD RegCtrl2; /* SCICR2 - Control register 2*/
DWORD RegClkICC; /* SCICLKICC - External Smart Card clock freq.*/
DWORD RegBaudValue; /* SCIVALUE - Cycles of baud rate clock*/
DWORD RegBaud; /* SCIBAUD - Baud rate clock*/
DWORD RegTide; /* SCITIDE - FIFO tide mark register*/
DWORD RegDMACtrl; /* SCIDMACR - DMA control register*/
DWORD RegStable; /* SCISTABLE - Debounce Timer*/
DWORD RegATime; /* SCIATIME - Activation Event time*/
DWORD RegDTime; /* SCIDTIME - Deactivation Event time*/
DWORD RegATRSTime; /* SCIATRSTIME - Time to start of ATR reception*/
DWORD RegATRDTime; /* SCIATRDTIME - Maximum ATR duration*/
DWORD RegStopTime; /* SCISTOPTIME - Duration before the card clock can be stopped*/
DWORD RegStartTime; /* SCISTARTTIME - Duration before transactions can commence*/
DWORD RegRetry; /* SCIRETRY - Retry Limit register*/
DWORD RegChTimeLS; /* SCICHTIMELS - Character timeout least sig 16 bits*/
DWORD RegChTimeMS; /* SCICHTIMEMS - Character timeout most sig 16 bits*/
DWORD RegBlkTimeLS; /* SCIBLKTIMELS - Receive timeout between blocks least sig 16 bits*/
DWORD RegBlkTimeMS; /* SCIBLKTIMEMS - Receive timeout between blocks most sig 16 bits*/
DWORD RegChGuard; /* SCICHGUARD - Character guard time*/
DWORD RegBlkGuard; /* SCIBLKGUARD - Block guard time*/
DWORD RegRxTime; /* SCIRXTIME - Receive timeout register*/
DWORD RegFlag; /* SCIFIFOSTATUS - FIFO status register*/
DWORD RegTxCount; /* SCITXCOUNT - Transmit FIFO count*/
DWORD RegRxCount; /* SCIRXCOUNT - Receive FIFO count*/
DWORD RegIntMask; /* SCIIMSC - Interrupt Enable mask set or clear*/
DWORD RegIntRaw; /* SCIRIS - Raw interrupt status*/
DWORD RegIntStatus; /* SCIMIS - Masked interrupt status*/
DWORD RegIntClear; /* SCIICR - Interrupt clear register*/
DWORD RegSyncAct; /* SCISYNCACT - Direct access to Smartcard signals*/
DWORD RegSyncData; /* SCISYNCTX - Smartcard input/output and clock signals*/
DWORD RegSyncRaw; /* SCISYNCRX - Raw IO and clock status*/
} PL131_sReg, *psci;
// Intr mask/set register bits
#define SCI0_CARD_INIM 0x0001
// Intr status register bits
#define SCI0_CARD_INIS 0x0001
// Status register bits
#define SCI0_CARD_PRESENT 0x400 // Card present
// Interrupt register bits
#define SCI0_CARDOUTIM 0x002 // Card removed
// Default values for Smartcard setup parameters (see ISO7816)
#define SCI0_DEF_RETRY 0 // Retry limit
#define SCI0_DEF_RXTIME 24000 // Receive timeout - *1ms
#define SCI0_DEF_STABLE 36 // Debounce time = 150ms (24MHz clock, 4.17mS steps)
#define SCI0_DEF_ATIME 42500 // Activation time 42500 cycles (40000 min)
#define SCI0_DEF_DTIME 5280 // Deactivation time 220us (5280 / 48MHz) 应该是220us,而不是(5280 / 48MHz)
#define SCI0_DEF_ATRSTIME 40000 // ATR start within 40000 cycles
#define SCI0_DEF_ATRDTIME 19200 // ATR complete within 19200 cycles
#define SCI0_DEF_STOPTIME 2000 // Clock stop time 2000 cycles (1860 min)
#define SCI0_DEF_STARTTIME 1000 // Clock start time 1000 cycles (700 min)
#define SCI0_DEF_BLKTIMEMS 0 // Receive timeout between blocks *40000 (not applicable to ATR)
#define SCI0_DEF_BLKTIMELS 40000
#define SCI0_DEF_CHTIMEMS 0 // Char interval 9600 etu's
#define SCI0_DEF_CHTIMELS 9600
#define SCI0_DEF_CLKICC 11// 47 // External clock frequency 250KHz (24MHz / (47 + 1) * 2)
#define SCI0_DEF_BAUD 0x6F8// 7140 // Baud rate clock
#define SCI0_DEF_VALUE 5 // SCI Baud cycles
#define SCI0_DEF_CHGUARD 0 // Character to character guard time
#define SCI0_DEF_BLKGUARD 0 // Block guard time //////////////////4
#define SCI0_DEF_SYNCTX 0 // TX sync clock and data
#define SCI0_DEF_SYNCRX 0 // RX sync clock and data
// Misc. timeouts
#define SCI0_TIMER_INSERT 500 // Time for card insert to be detected (5 seconds)
#define SCI0_TIMER_ACK 250 // Time for card to send back all data after reset (2.5 seconds)
/*
* Description:
* FIFO sizes
*/
#define PL131_FIFO_SIZE_TX ((unsigned long) 8)
#define PL131_FIFO_SIZE_RX ((unsigned long) 8)
BOOL SCI_DllEntry ( HINSTANCE hinstDll, DWORD dwReason, LPVOID lpReserved );
BOOL SCI_Close (DWORD hOpenContext);
BOOL SCI_Deinit (DWORD hDeviceContext);
DWORD SCI_Init (DWORD dwContext);
BOOL SCI_IOControl (DWORD hOpenContext, DWORD dwCode);
DWORD SCI_Open (DWORD hDeviceContext, DWORD AccessCode, DWORD ShareMode);
void SCI_PowerDown(DWORD hDeviceContext);
void SCI_PowerUp (DWORD hDeviceContext);
DWORD SCI_Read (DWORD hOpenContext, LPVOID pBuffer, DWORD Count);
DWORD SCI_Seek (DWORD hOpenContext, long Amount, WORD Type);
DWORD SCI_Write (DWORD hOpenContext, LPCVOID pSourceBytes, DWORD NumberOfBytes);
static BOOL InitializeDevice( );
void DEBUGPUT ( );
void CardActive ( );
DWORD SCR_ISTthread(PSMARTCARD_EXTENSION smartcardExtension);
void Clean( );
////////////////////////////////////////////////////////////////////////////////////////////////
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