📄 dma1.h
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#ifndef _MMCIDMA_H
#define _MMCIDMA_H
#include <pkfuncs.h>
#include <winioctl.h>
#include <platform.h>
#define DMAC_BASE PHYS_DMA_BASE
// DMA Regs
/*
#define SYS_DMAPSR0 ((volatile int *)0x10000064)
#define SYS_DMAPSR1 ((volatile int *)0x10000068)
#define SYS_DMAPSR2 ((volatile int *)0x1000006c)
*/
typedef unsigned long DWORD;
//typedef short WORD;
typedef struct tagDMACRegisters {
DWORD DMACIntStatus; // DMAC_BASE
DWORD DMACIntTCStatus; // DMAC_BASE + 0x004
DWORD DMACIntTCClear; // DMAC_BASE + 0x008
DWORD DMACIntErrorStatus; // DMAC_BASE + 0x00C
DWORD DMACIntErrClr; // DMAC_BASE + 0x010
DWORD DMACRawIntTCStatus; // DMAC_BASE + 0x014
DWORD DMACRawIntErrorStatus; // DMAC_BASE + 0x018
DWORD DMACEnbldChns; // DMAC_BASE + 0x01C
DWORD DMACSoftBReq; // DMAC_BASE + 0x020
DWORD DMACSoftSReq; // DMAC_BASE + 0x024
DWORD DMACSoftLBReq; // DMAC_BASE + 0x028
DWORD DMACSoftLSReq; // DMAC_BASE + 0x02C
DWORD DMACConfiguration; // DMAC_BASE + 0x030
DWORD DMACSync; // DMAC_BASE + 0x034
DWORD Padding1[50]; // DMAC_BASE + 0x038
DWORD DMACC0SrcAddr; // DMAC_BASE + 0x100
DWORD DMACC0DestAddr; // DMAC_BASE + 0x104
DWORD DMACC0LLI; // DMAC_BASE + 0x108
DWORD DMACC0Control; // DMAC_BASE + 0x10C
DWORD DMACC0Configuration; // DMAC_BASE + 0x110
DWORD Padding2[3]; // DMAC_BASE + 0x114
DWORD DMACC1SrcAddr; // DMAC_BASE + 0x120
DWORD DMACC1DestAddr; // DMAC_BASE + 0x124
DWORD DMACC1LLI; // DMAC_BASE + 0x128
DWORD DMACC1Control; // DMAC_BASE + 0x12C
DWORD DMACC1Configuration; // DMAC_BASE + 0x130
DWORD Padding3[3]; // DMAC_BASE + 0x134
DWORD DMACC2SrcAddr; // DMAC_BASE + 0x140
DWORD DMACC2DestAddr; // DMAC_BASE + 0x144
DWORD DMACC2LLI; // DMAC_BASE + 0x148
DWORD DMACC2Control; // DMAC_BASE + 0x14C
DWORD DMACC2Configuration; // DMAC_BASE + 0x150
DWORD Padding4[3]; // DMAC_BASE + 0x154
DWORD DMACC3SrcAddr; // DMAC_BASE + 0x160
DWORD DMACC3DestAddr; // DMAC_BASE + 0x164
DWORD DMACC3LLI; // DMAC_BASE + 0x168
DWORD DMACC3Control; // DMAC_BASE + 0x16C
DWORD DMACC3Configuration; // DMAC_BASE + 0x170
DWORD Padding5[3]; // DMAC_BASE + 0x174
DWORD DMACC4SrcAddr; // DMAC_BASE + 0x180
DWORD DMACC4DestAddr; // DMAC_BASE + 0x184
DWORD DMACC4LLI; // DMAC_BASE + 0x188
DWORD DMACC4Control; // DMAC_BASE + 0x18C
DWORD DMACC4Configuration; // DMAC_BASE + 0x190
DWORD Padding6[3]; // DMAC_BASE + 0x194
DWORD DMACC5SrcAddr; // DMAC_BASE + 0x1A0
DWORD DMACC5DestAddr; // DMAC_BASE + 0x1A4
DWORD DMACC5LLI; // DMAC_BASE + 0x1A8
DWORD DMACC5Control; // DMAC_BASE + 0x1AC
DWORD DMACC5Configuration; // DMAC_BASE + 0x1B0
DWORD Padding7[3]; // DMAC_BASE + 0x1B4
DWORD DMACC6SrcAddr; // DMAC_BASE + 0x1C0
DWORD DMACC6DestAddr; // DMAC_BASE + 0x1C4
DWORD DMACC6LLI; // DMAC_BASE + 0x1C8
DWORD DMACC6Control; // DMAC_BASE + 0x1CC
DWORD DMACC6Configuration; // DMAC_BASE + 0x1D0
DWORD Padding8[3]; // DMAC_BASE + 0x1D4
DWORD DMACC7SrcAddr; // DMAC_BASE + 0x1E0
DWORD DMACC7DestAddr; // DMAC_BASE + 0x1E4
DWORD DMACC7LLI; // DMAC_BASE + 0x1E8
DWORD DMACC7Control; // DMAC_BASE + 0x1EC
DWORD DMACC7Configuration; // DMAC_BASE + 0x1F0
DWORD Padding9[891]; // DMAC_BASE + 0x1F4
DWORD DMACPeriphID0; // DMAC_BASE + 0xFE0
DWORD DMACPeriphID1; // DMAC_BASE + 0xFE4
DWORD DMACPeriphID2; // DMAC_BASE + 0xFE8
DWORD DMACPeriphID3; // DMAC_BASE + 0xFEC
DWORD DMACCellID0; // DMAC_BASE + 0xFF0
DWORD DMACCellID1; // DMAC_BASE + 0xFF4
DWORD DMACCellID2; // DMAC_BASE + 0xFF8
DWORD DMACCellID3; // DMAC_BASE + 0xFFC
}DMAC_REGS, *PDMAC_REGS;
#define DMAC_CONFIG_E 0x0001 // DMA controller enable
typedef struct tagDMAChannelRegs {
DWORD DMACCxSrcAddr; // Channel base + 0x00
DWORD DMACCxDestAddr; // Channel base + 0x04
DWORD DMACCxLLI; // Channel base + 0x08
DWORD DMACCxControl; // Channel base + 0x0C
DWORD DMACCxConfiguration; // Channel base + 0x10
}DMAC_CHANNEL_REGS, *PDMAC_CHANNEL_REGS;
typedef struct tagLLIEntry *PLLI_ENTRY;
// LLI list entry structure
typedef struct tagLLIEntry {
DWORD dwSourceAddress;
DWORD dwDestAddress;
PLLI_ENTRY pNextEntry;
DWORD dwControl;
}LLI_ENTRY, *PLLI_ENTRY;
// DMAC channel config register
#define DMAC_CHCONFIG_H 0x00040000 // Halt transfer
#define DMAC_CHCONFIG_A 0x00020000 // Channel is active
#define DMAC_CHCONFIG_L 0x00010000 // Lock transfer
#define DMAC_CHCONFIG_ITC 0x00008000 // Terminal count interrupt enable
#define DMAC_CHCONFIG_IE 0x00004000 // Error interrupt enable
#define DMAC_CHCONFIG_FLOW 0x00003800 // Flow control
#define DMAC_CHCONFIG_DPER 0x000003C0 // Destination peripheral
#define DMAC_CHCONFIG_SPER 0x0000001E // Source peripheral
#define DMAC_CHCONFIG_E 0x00000001 // Channel enable
// DMAC channel control register bit masks
#define DMAC_CTRL_I 0x80000000 // Terminal count interrupt enable
#define DMAC_CTRL_CACHE 0x40000000 // Cacheable
#define DMAC_CTRL_BUF 0x20000000 // Bufferable
#define DMAC_CTRL_PRIV 0x10000000 // Privileged
#define DMAC_CTRL_DI 0x08000000 // Destination increment
#define DMAC_CTRL_SI 0x04000000 // Source increment
#define DMAC_CTRL_D 0x02000000 // Dest master select
#define DMAC_CTRL_S 0x01000000 // Source master select
#define DMAC_DWIDTH 0x00E00000 // Destination width
#define DMAC_SWIDTH 0x001C0000 // Source width
#define DMAC_DBSIZE 0x00038000 // Dest burst size
#define DMAC_SBSIZE 0x00007000 // Source burst size
#define DMAC_TRANSFER_SIZE 0x00000FFF // Transfer size
// These are the transfer width ids
#define TRANSFER_WIDTH_BYTE 0x000
#define TRANSFER_WIDTH_WORD 0x001
#define TRANSFER_WIDTH_DWORD 0x002
#define DMAC_DWIDTH_SHIFT 21
#define DMAC_SWIDTH_SHIFT 18
#define DMAC_DBSIZE_SHIFT 15
#define DMAC_SBSIZE_SHIFT 12
// These are the burst size ids
#define BURST_SIZE_1 0x000
#define BURST_SIZE_4 0x001
#define BURST_SIZE_8 0x002
#define BURST_SIZE_16 0x003
#define BURST_SIZE_32 0x004
#define BURST_SIZE_64 0x005
#define BURST_SIZE_128 0x006
#define BURST_SIZE_256 0x007
#define DMAC_FLOW_SHIFT 11
#define DMAC_DPER_SHIFT 6
#define DMAC_SPER_SHIFT 1
#define FLOW_MEM_MEM_DMAC 0x000 // Memory to memory - DMAC as flow controller
#define FLOW_MEM_PER_DMAC 0x001 // Memory to peripheral - DMAC as flow controller
#define FLOW_PER_MEM_DMAC 0x002 // Peripheral to memory - DMAC as flow controller
#define FLOW_PER_PER_DMAC 0x003 // Peripheral to peripheral - DMAC as flow controller
#define FLOW_PER_PER_DEST 0x004 // Peripheral to peripheral - destination peripheral as flow controller
#define FLOW_MEM_PER_DEST 0x005 // Memory to peripheral - destination peripheral as flow controller
#define FLOW_PER_MEM_SOURCE 0x006 // Peripheral to memory - source peripheral as flow controller
#define FLOW_PER_PER_SOURCE 0x007 // Peripheral to peripheral - source peripheral as flow controller
typedef volatile struct TAG_SP810_REGS
{
DWORD SCCTRL; /* 0x0 System Control register */
DWORD SCSYSSTAT; /* 0x4 System Status Register register */
DWORD SCIMCTRL; /* 0x8 Interrupt Mode Control register */
DWORD SCIMSTAT; /* 0xC Interrupt Mode Status register */
DWORD SCXCTRL; /* 0x10 Crystal Control register */
DWORD SCPLLCTRL; /* 0x14 PLL Control register */
DWORD SCPLLFCTRL; /* 0x18 PLL Frequency Control register */
DWORD SCPERCTRL0; /* 0x1C Peripheral Control register 0 */
DWORD SCPERCTRL1; /* 0x20 Peripheral Control register 1 */
DWORD SCPEREN; /* 0x24 Peripheral Clock Enable register */
DWORD SCPERDIS; /* 0x28 Peripheral Clock Disable register */
const DWORD SCPERCLKEN; /* 0x2C Peripheral Clock Enable Status register */
const DWORD SCPERSTAT; /* 0x30 Peripheral Clock Status register */
} vstSP810Regs, *pvstSP810Regs;
/*
* Peripheral Clock Enable Signal definitions - used when enabling and
* disabling peripheral clocks via the SP810 System Controller
*/
#define HCLKDMA 0x1
int CFMemoryCopyByDma(void);
int CFSendDataToDeviceByDma(void);
#endif
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