lmisettings.h

ARM9基于WINDOWSCE的BSP源代码

/******************************************************************************/
/* Copyright (C), 2003-2004, Shanghai Jade Technologies Co., Ltd.             */
/* File name: lmisettings.h                                                   */
/* Description:                                                               */
/*    LMI reg structure and reg bits definition                              */
/* Version: Original version.                                                 */
/* History:                                                                   */
/*   <author>        <time>      <version>       <desc>                       */
/*    Wang Wei      20/12/04        1.0         create                        */                         
/******************************************************************************/

#ifndef _LMISET_H
#define _LMISET_H

#include "bitctrl.h"

/**LMICONFIG************************************/
//enable LMI
#define bwLMI_CFG_ENABLE 1
#define bsLMI_CFG_ENABLE 0

//mode 6800 or 8080
#define bwLMI_CFG_MODE 2
#define bsLMI_CFG_MODE 1

//LMIWR is low or high when asserted. 1 is low,0 is high when asserted.
#define bwLMI_CFG_WRINV 1
#define bsLMI_CFG_WRINV 3

//LIMIRD is when asserted
#define bwLMI_CFG_RDINV 1
#define bsLMI_CFG_RDINV 4

//LMIDE is when asserted
#define bwLMI_CFG_DEINV 1
#define bsLMI_CFG_DEINV 5

//LMIDIR is ? when asserted
#define bwLMI_CFG_DIRINV 1
#define bsLMI_CFG_DIRINV 6

//LMICs is ? when asserted
#define bwLMI_CFG_CSINV 1
#define bsLMI_CFG_CSINV 7

//LMIDIR output 0 or 1 when there is no LMI access.
#define bwLMI_CFG_DEFDIR 1
#define bsLMI_CFG_DEFDIR 8

//buswidth:  0 LMI bus is half size of DateWidth,otherwise width.
#define bwLMI_CFG_BUSWIDTH 1
#define bsLMI_CFG_BUSWIDTH 9

//Datawidth 0 --16 bits,1 --- 18bits.
#define bwLMI_CFG_DATAWIDTH 1
#define bsLMI_CFG_DATAWIDTH 10

/*******LMITIM0*************************/

//LMIRD assert period RDBP+1
#define bwLMI_TIM0_RDBP 7
#define bsLMI_TIM0_RDBP 0

//width of LMIRD pulse RDWP+1
#define bwLMI_TIM0_RDWP 7
#define bsLMI_TIM0_RDWP 8

//period of LMIWR  WRBP+1
#define bwLMI_TIM0_WRBP 7
#define bsLMI_TIM0_WRBP 16

//width of LMIWR pulse
#define bwLMI_TIM0_WRWP 7
#define bsLMI_TIM0_WRWP 24

/*******LMITIM1*************************/
/*The timing parameter of LMIRD/DE are determined by RdBP and RdWP */
/*when LMI is configured to 8080 or user define 8080 mode, */
/*by DeBP and DeWP when LMI is configured to 6800 or user define 6800 mode.*/
//LMIDE deassert period deBP+1
#define bwLMI_TIM1_DEBP 7
#define bsLMI_TIM1_RDBP 0

//width of LMIDE pulse RDWP+1
#define bwLMI_TIM1_DEWP 7
#define bsLMI_TIM1_DEWP 8

//period of LMIRD  WRBP+1
#define bwLMI_TIM1_CSBP 7
#define bsLMI_TIM1_CSBP 16

//width of LMIRD pulse
#define bwLMI_TIM1_CSWP 8   //??
#define bsLMI_TIM1_CSWP 24


/**********LMITIM2*************************/
//rdst set the LMIRDATE smapletime. RdST+1 LMICLK cycles.
#define bwLMI_TIM2_RDST 7
#define bsLMI_TIM2_RDST 0

//axsw set the LMI access time. AxsW+1 LMICLK cycles.
#define bwLMI_TIM2_AXSW 7
#define bsLMI_TIM2_AXSW 8

/*****LMIRIS raw intterupt */
/*can also be used as MIS ,intmask and IntClear reg.**************/

// single LMI access raw int. asserts when access finish.
#define bwLMI_RIS_SREQ 1  
#define bsLMI_RIS_SREQ 0
// burst LMI access raw int. when access finish.
#define bwLMI_RIS_BREQ 1  
#define bsLMI_RIS_BREQ 1

//TX FIFO error RIS
#define bwLMI_RIS_TXFERR 1  
#define bsLMI_RIS_TxFERR 2

//TX FIFO flag RIS
#define bwLMI_RIS_TXFFLAG 1  
#define bsLMI_RIS_TXFFLAG 3

//RX FIFO error RIS
#define bwLMI_RIS_RXFERR 1  
#define bsLMI_RIS_RXFERR 4

//TX FIFO flag RIS
#define bwLMI_RIS_RXFFLAG 1  
#define bsLMI_RIS_RXFFLAG 5

/******LMISTATUS**************************************/
//bus busy
#define bwLMI_STATUS_BUSBUSY 1
#define bsLMI_STATUS_BUSBUSY 0

//single mode
#define bwLMI_STATUS_SINGLE 1
#define bsLMI_STATUS_SINGLE 1

//burst mode ?
#define bwLMI_STATUS_BURST 1
#define bsLMI_STATUS_BURST 2

//waiting for EBI
#define bwLMI_STATUS_WAITEBI 1
#define bsLMI_STATUS_WAITEBI 3


/***********************B DATA*********/
#define bwLMI_BDATA  16
#define bsLMI_BDATA  0

/******************BCTRL burst control reg*************/
//enable LMI burst mode
#define bwLMI_BCTRL_BREQ 1
#define bsLMI_BCTRL_BREQ 0

//1-burst write ,0-burst read
#define bwLMI_BCTRL_RW 1
#define bsLMI_BCTRL_RW 1

//burst write conversion enable
#define bwLMI_BCTRL_TXCONV 1
#define bsLMI_BCTRL_TXCONV 2

//burst read conversion enable
#define bwLMI_BCTRL_RXCONV 1
#define bsLMI_BCTRL_RXCONV 3

/******************burst config reg***************/
//burst mode : 0x no change LMI address,10 Decrease ,11 Increase when processing burst
#define bwLMI_BCFG_MODE 2
#define bsLMI_BCFG_MODE 0

//step of address
#define bwLMI_BCFG_STEP 6
#define bsLMI_BCFG_STEP 2

//big-endian TX input data.
#define bwLMI_BCFG_TXBEIN 1
#define bsLMI_BCFG_TXBEIN 8
//rgb mode of Tx input data 0-rgb 1555,1-rgb565
#define bwLMI_BCFG_TXRGBIN 1
#define bsLMI_BCFG_TXRGBIN 9

//exchange red blue bits of TX data
#define bwLMI_BCFG_TXRBXCHG 1
#define bsLMI_BCFG_TXRBXCHG 10

//reg mode of Tx output
#define bwLMI_BCFG_TXRGBOUT 1
#define bsLMI_BCFG_TXRGBOUT 11

//big-endian TX output data.
#define bwLMI_BCFG_TXBEOUT 1
#define bsLMI_BCFG_TXBEOUT 12

//common bright bit for RGB1555
#define bwLMI_BCFG_TXBRI 1
#define bsLMI_BCFG_TXBRI 13

//big-endian RX input data.
#define bwLMI_BCFG_RXBEIN 1
#define bsLMI_BCFG_RXBEIN 14

//rgb mode of Rx input data 0-rgb 1555,1-rgb565
#define bwLMI_BCFG_RXRGBIN 1
#define bsLMI_BCFG_RXRGBIN 15

//exchange red blue bits of RX data
#define bwLMI_BCFG_RXRBXCHG 1
#define bsLMI_BCFG_RXRBXCHG 16

//reg mode of Rx output 0-RGB1555,1-RGB565
#define bwLMI_BCFG_RXRGBOUT 1
#define bsLMI_BCFG_RXRGBOUT 17

//big-endian RX output data.
#define bwLMI_BCFG_RXBEOUT 1
#define bsLMI_BCFG_RXBEOUT 18

//common bright bit for RGB1555 output
#define bwLMI_BCFG_RXBRI 1
#define bsLMI_BCFG_RXBRI 19

/*********burst number*********/
#define bwLMI_BNUM 16
#define bsLMI_BNUM 0

/***********burst base*********/
#define bwLMI_BBASE 16
#define bsLMI_BBASE 0

/*********DMACTRL************/
#define bwLMI_DMACTRL_TxEN 1
#define bsLMI_DMACTRL_TxEN 0

#define bwLMI_DMACTRL_RxEN 1
#define bsLMI_DMACTRL_RxEN 1

#define bwLMI_DMACTRL_SIZE 6
#define bsLMI_DMACTRL_SIZE 2

#define bwLMI_DMACTRL_TXFWMARK 4
#define bsLMI_DMACTRL_TXFWMARK 8

#define bwLMI_DMACTRL_RXFWMARK 4
#define bsLMI_DMACTRL_RXFWMARK 12

/***************Current address*********/
#define bwLMI_CURADDR 16  
#define bsLMI_CURADDR 0

/***************FIFO control*********/
#define bwLMI_FCTRL_TXCLR 1  //clear FIFO data
#define bsLMI_FCTRL_TXCLR 0

#define bwLMI_FCTRL_RXCLR 1
#define bsLMI_FCTRL_RXCLR 1

/************FIFO status*************/
//Tx FIFO under run
#define bwLMI_FSTATUS_TXFUR  1   
#define bsLMI_FSTATUS_TXFUR  0

 //Tx FIFO empty
#define bwLMI_FSTATUS_TXFE  1   
#define bsLMI_FSTATUS_TXFE  1

//Tx FIFO almost empty (<=1)
#define bwLMI_FSTATUS_TXFAE  1   
#define bsLMI_FSTATUS_TXFAE  2

//Tx FIFO half full
#define bwLMI_FSTATUS_TXFHF  1   
#define bsLMI_FSTATUS_TXFHF  3

//Tx FIFO flag
#define bwLMI_FSTATUS_TXFFLAG  1   
#define bsLMI_FSTATUS_TXFFLAG  4

//Tx FIFO almost full (>=15)
#define bwLMI_FSTATUS_TXFAF  1   
#define bsLMI_FSTATUS_TXFAF  5

//Tx FIFO full
#define bwLMI_FSTATUS_TXFF  1   
#define bsLMI_FSTATUS_TXFF  6

//Tx FIFO overflow
#define bwLMI_FSTATUS_TXFOV  1   
#define bsLMI_FSTATUS_TXFOV  7

//TX fifo fill level
#define bwLMI_FSTATUS_TXFLEVEL  5   
#define bsLMI_FSTATUS_TXFLEVEL  8
///////////////////////////////////////////RX
//RX FIFO under run
#define bwLMI_FSTATUS_RXFUR  1   
#define bsLMI_FSTATUS_RXFUR  16

 //RX FIFO empty
#define bwLMI_FSTATUS_RXFE  1   
#define bsLMI_FSTATUS_RXFE  17

//RX FIFO almost empty (<=1)
#define bwLMI_FSTATUS_RXFAE  1   
#define bsLMI_FSTATUS_RXFAE  18

//RX FIFO half full
#define bwLMI_FSTATUS_RXFHF  1   
#define bsLMI_FSTATUS_RXFHF  21

//RX FIFO flag
#define bwLMI_FSTATUS_RXFFLAG  1   
#define bsLMI_FSTATUS_RXFFLAG  19

//RX FIFO almost full (>=15)
#define bwLMI_FSTATUS_RXFAF  1   
#define bsLMI_FSTATUS_RXFAF  20

//RX FIFO full
#define bwLMI_FSTATUS_RXFF  1   
#define bsLMI_FSTATUS_RXFF  22

//RX FIFO overflow
#define bwLMI_FSTATUS_RXFOV  1   
#define bsLMI_FSTATUS_RXFOV  23

//RX fifo fill level
#define bwLMI_FSTATUS_RXFLEVEL  5   
#define bsLMI_FSTATUS_RXFLEVEL  24







#endif