gpiodrv.h

ARM9基于WINDOWSCE的BSP源代码

/*
 * ------------------------
 *
 * Jade chip 
 *
 * ------------------------
 * File:     gpiodrv.h,v
 * Revision: 1.1
 * ----------------------------------------------------------------
 * $
 */
#include <windows.h>


// These defines determine which GPIO devices should be accessed
//#define GPIO2   TRUE
//#define GPIO3 TRUE
//#define GPIO4 TRUE

#define DWORD unsigned long

#define GPIO1_BASE  PHYS_GPIO5_BASE
#define GPIO2_BASE  PHYS_GPIO6_BASE
#define GPIO3_BASE  PHYS_GPIO2_BASE
#define GPIO4_BASE  PHYS_GPIO3_BASE

#define GPIO1_PIN_MASK  0x000000FF
#define GPIO2_PIN_MASK  0x0000FF00
#define GPIO3_PIN_MASK  0x00FF0000
#define GPIO4_PIN_MASK  0xFF000000

typedef struct tagGPIORegisters {
    DWORD   GPIOData5;               // GPIO_BASE
    DWORD   Padding1[255];          // GPIO_BASE + 0x004
    DWORD   GPIODir5;                // GPIO_BASE + 0x400
    DWORD   GPIOIS5;                 // GPIO_BASE + 0x404
    DWORD   GPIOIBE5;                // GPIO_BASE + 0x408
    DWORD   GPIOIEV5;                // GPIO_BASE + 0x40C
    DWORD   GPIOIE5;                 // GPIO_BASE + 0x410
    DWORD   GPIORIS5;                // GPIO_BASE + 0x414
    DWORD   GPIOMIS5;                // GPIO_BASE + 0x418
    DWORD   GPIOIC5;                 // GPIO_BASE + 0x41C
    DWORD   GPIOAFSEL5;              // GPIO_BASE + 0x420

    DWORD   Padding2[751];          // GPIO_BASE + 0x424

    DWORD   GPIOPeriphID0;          // GPIO_BASE + 0xFE0
    DWORD   GPIOPeriphID1;          // GPIO_BASE + 0xFE4
    DWORD   GPIOPeriphID2;          // GPIO_BASE + 0xFE8
    DWORD   GPIOPeriphID3;          // GPIO_BASE + 0xFEC

    DWORD   GPIOCellID0;            // GPIO_BASE + 0xFF0
    DWORD   GPIOCellID1;            // GPIO_BASE + 0xFF4
    DWORD   GPIOCellID2;            // GPIO_BASE + 0xFF8
    DWORD   GPIOCellID3;            // GPIO_BASE + 0xFFC
}GPIO_REGS, *PGPIO_REGS;

typedef struct tagGpioInfo {
    DWORD               OpenCnt;    // @field Protects use of this port 
    HANDLE              hGpio1ISTThread;
    HANDLE              hGpio1ISTEvent;
    HANDLE              hGpio2ISTThread;
    HANDLE              hGpio2ISTEvent;
    HANDLE              hGpio3ISTThread;
    HANDLE              hGpio3ISTEvent;
    HANDLE              hGpio4ISTThread;
    HANDLE              hGpio4ISTEvent;
    DWORD               dwAllocatedPinMask; // total IO pins currently allocated
    BOOL                fGpio1ISTExit;
    BOOL                fGpio2ISTExit;
    BOOL                fGpio3ISTExit;
    BOOL                fGpio4ISTExit;
    volatile PGPIO_REGS pGpio1Regs;
    volatile PGPIO_REGS pGpio2Regs;
    volatile PGPIO_REGS pGpio3Regs;
    volatile PGPIO_REGS pGpio4Regs;
    CRITICAL_SECTION    csPort;
    LIST_ENTRY          OpenList;   // @field Head of linked list of OPEN_INFOs    
    CRITICAL_SECTION    OpenCS;     // @field Protects Open Linked List + ref counts
}GPIO_INFO, *PGPIO_INFO;

typedef struct tagGpioOpenInfo {
    PGPIO_INFO      pGpioHead;      // @field Pointer back to our GPIO_INFO
    DWORD           dwAllocatedPinMask;     // IO pins allocated to this instance
    DWORD           dwEventPinMask;
    HANDLE          hPinEvent;
    LONG            StructUsers;    // @field Count of threads currently using struct.
    LIST_ENTRY      llist;          // @field Linked list of OPEN_INFOs
}GPIO_OPEN_INFO, *PGPIO_OPEN_INFO;


/*
extern "C" DWORD Gpio1ISTThread(PVOID pvParam);
extern "C" DWORD Gpio2ISTThread(PVOID pvParam);
extern "C" DWORD Gpio3ISTThread(PVOID pvParam);
extern "C" DWORD Gpio4ISTThread(PVOID pvParam);
*/