lan91c96_adapter.h

ARM9基于WINDOWSCE的BSP源代码

/*
*
*
*Description
*              Hardware specific and driver datastructure declarations
*
*/
#ifndef __LAN91C96_ADAPTER__
#define __LAN91C96_ADAPTER__

//Windows CE debug zones
#define ZONE_INIT       	0
#define ZONE_INTR       	0
#define ZONE_RX         	0
#define ZONE_TX         	0
#define PrintDebugMsg    	//RETAILMSG

//NDIS Version Declaration
#ifdef NDIS50_MINIPORT
#define DRIVER_NDIS_MAJOR_VERSION 5	
#else
#define DRIVER_NDIS_MAJOR_VERSION 4
#endif
#define DRIVER_NDIS_MINOR_VERSION 0
#define DRIVER_NDIS_VERSION       ((DRIVER_NDIS_MAJOR_VERSION << 8) + DRIVER_NDIS_MINOR_VERSION)

//Multicast Table Entry Structure
#define MAX_MULTICAST_ADDRESS   128 

typedef struct 
{
    UINT  MulticastTableEntryCount;
    UCHAR MulticastTableEntry[MAX_MULTICAST_ADDRESS * ETH_LENGTH_OF_ADDRESS];
} MULTICAST_TABLE;

//The MAC receive context structure.
typedef struct  _MAC_RECEIVE_CONTEXT
{
    UINT            Range;          //  Packet size.
    UCHAR           *PacketData;    //  User data.
} MAC_RECEIVE_CONTEXT;
#define MAC_RECEIVE_CONTEXT_SIZE    sizeof(MAC_RECEIVE_CONTEXT)

typedef struct  _MINIPORT_PACKET
{
    struct _MINIPORT_PACKET *Next;       //  Next packet on queue.
    UCHAR                   PacketNumber;//  Adapter Packet number.
    USHORT					PacketRange;
} MINIPORT_PACKET;

typedef struct _MINIPORT_PACKET_QUE
{
    MINIPORT_PACKET  *First;             //  First packet on queue or 0
    MINIPORT_PACKET  *Last;              //  Last packet on queue or &First
} MINIPORT_PACKET_QUE;
#define MAC_PACKET_QUE_SIZE sizeof(MAC_PACKET_QUE)

//Clear packet queue macro.
#define ClearPacketQue(Que) {(Que).First = (MINIPORT_PACKET *) 0;                \
    (Que).Last  = (MINIPORT_PACKET *) &(Que).First;}    \

//Add a packet to queue macro.
#define QuePacket(Que, _Packet)  {MINIPORT_PACKET *__Last = (Que).Last;   \
    _Packet->Next = (MINIPORT_PACKET *) 0;   \
__Last->Next = (Que).Last = _Packet;}

//Remove a packet from queue macro.
#define DequePacket(Que, Packet) {Packet = (Que).First;                                \
    if(((Que).First = Packet->Next) == (MINIPORT_PACKET *) 0) \
(Que).Last = (MINIPORT_PACKET *) &(Que).First;}        

#define TOTAL_BUFFER_SIZE	0x2000
#define MAX_LOOKAHEAD_SIZE      1500
#define LOOK_AHEAD_BUFFER_SIZE  2048
#define MINIPORT_ADAPTER_SIZE   sizeof(MINIPORT_ADAPTER)
#define MAX_FRAME_DATA_SIZE     1500
#define MAX_FRAME_SIZE          ((USHORT)1514)
#define MIN_FRAME_SIZE          14
#define MIN_LEGAL_FRAME_SIZE    64
#define ETHERNET_HEADER_SIZE    14
#define MAC_ADDRESS_SIZE		6
#define MAX_MULTICAST_ADDRESS   128

#define DEFAULT_IO_BASE         0x300   //  Platform Specific
#define DEFAULT_IRQ             10      //  Platform Specific

//--------------------- DRIVER STRUCTURE --------------------------------
typedef  struct _MINIPORT_ADAPTER
{
    NDIS_HANDLE             AdapterHandle;
    ULONG					IOBase;				//  Platform Specific - type might have to be changed to accomodate platform specific values
    BOOLEAN                 IsPortRegistered;   //  I/O Port registere with NdisMRegisterIORage (...)
    NDIS_MINIPORT_INTERRUPT InterruptInfo;      //  From NdisMRegisterInterrupt(..)
    USHORT                  InterruptLevel;     //  IRQ in use
    BOOLEAN                 IsInterruptSet;     //  Attached to interrupt using NdisMRegisterInterrupt(...)
    USHORT					InterruptVector;
    USHORT					InterruptType;
    USHORT                  BusType;
    USHORT                  BusNumber;
    USHORT					ConfigReg;          //  Config register to be output
    USHORT					ChipID;				//  Chip ID 
    USHORT					ChipRev;			//  Chip Revision
    
    UCHAR                   *LookAheadBuffer;   //  Pointer to lookahead buffer
    UCHAR                   *TxBuffer;          //  Pointer to the TX Copy buffer
    USHORT                  State;              //  Current state of the Adapter..
    NDIS_OID                LookAhead;          //  Max lookahead size
    UCHAR                   Duplex;				//  Duplex ?? FDX/HDX
    USHORT			        MACAddress[3];		//  Current Station address
    UCHAR                   HashTable[8];       //  Multicast hash bits
    USHORT                  RCR;                //  Updated Receive Control Register.
    USHORT					TCR;				//  Updated Transmit Control Register.
    USHORT					CtrlRegister;
    
    USHORT					LinkStatus;			//  Link Status
    BOOLEAN					NeedIndComplete;	//	Recieve Complete indication
    BOOLEAN					RCVBroadcast;		//	If set recvs broadcasts.
    BOOLEAN					RCVAllMulticast;	//  Rcv All multicasts.
    BOOLEAN					PromiscuousMode;
    MULTICAST_TABLE			MulticastTable;		//	Multicast Table
    BOOLEAN                 TxResPending;       //  When set, NDISMResourceAvailable should be called
    MINIPORT_PACKET_QUE     AckPending;         //  Waiting completion intr
	BOOLEAN					AllocIntPending;	//  When TRUE, alloc intr., in process
	MINIPORT_PACKET_QUE		AllocPending;		//  Holds the packet for which alloc is in progress
    
    //Required Statistics.
    UINT					Stat_TxOK;
    UINT					Stat_RxOK;
    UINT					Stat_TxError;
    UINT					Stat_RxError;
    UINT					Stat_RxOvrn;
    UINT					Stat_AlignError;
    UINT					Stat_SingleColl;
    UINT					Stat_MultiColl;
    
}MINIPORT_ADAPTER, *PMINIPORT_ADAPTER, *PSMSC_ADAPTER;


//-----------------  LAN91C96 Chip Specific Registry Declarations ---------
#define CHIPID_LAN91C96		    4
#define BANK_ID_MASK            0xff00  //  Mask constant part of bank register
#define BANK_UPPER              0x3300  //  Constant value for upper byte of bank register
#define BANK_MASK               (BANK_UPPER | 3)

#define ADDR_OFFSET(REG)       (REG)				//  Use this to offset the registers

#define BANK_SELECT             ADDR_OFFSET(14)      //  Offset in IO space to Bank select

//Bank 0 Registers
#define BANK0_TCR               ADDR_OFFSET(0)       //  Transmit control register
#define BANK0_STS               ADDR_OFFSET(2)       //  EPH status register 
#define BANK0_RCR               ADDR_OFFSET(4)       //  Receive control register
#define BANK0_CTR               ADDR_OFFSET(6)       //  Statistics counter register
#define BANK0_MIR               ADDR_OFFSET(8)       //  Memory information register
#define BANK0_MCR               ADDR_OFFSET(10)       //  Memory configuration register
#define BANK0_RES               ADDR_OFFSET(12)      //  Reserved

//Bank 1 Registers
#define BANK1_CONFIG            ADDR_OFFSET(0)       //  Adapter configuration register
#define BANK1_BASE              ADDR_OFFSET(2)       //  IO Base address
#define BANK1_IA0               ADDR_OFFSET(4)       //  Current address bytes 0-1
#define BANK1_IA2               ADDR_OFFSET(6)       //  Current address bytes 2-3
#define BANK1_IA4               ADDR_OFFSET(8)       //  Current address bytes 4-5
#define BANK1_GEN               ADDR_OFFSET(10)      //  General purpose
#define BANK1_CTL               ADDR_OFFSET(12)      //  Control

//Bank 2 Registers
#define BANK2_MMUCMD            ADDR_OFFSET(0)       //  MMU command register
#define BANK2_AUTOTX            ADDR_OFFSET(1)
#define BANK2_PNR               ADDR_OFFSET(2)       //  Packet Number Register (8 bit)
#define BANK2_ARR               ADDR_OFFSET(3)       //  Allocation Result Register (8 bit)
#define BANK2_FIFOS             ADDR_OFFSET(4)
#define BANK2_TX_FIFO           ADDR_OFFSET(4)       //  Transmit Fifo Port Register (8 bit)
#define BANK2_RX_FIFO           ADDR_OFFSET(5)       //  Receive Fifo Port Register (8 bit)
#define BANK2_PTR               ADDR_OFFSET(6)       //  Pointer Register
#define BANK2_DATA1             ADDR_OFFSET(8)       //  Data Register
#define BANK2_DATA2             ADDR_OFFSET(10)      //  Data Register
#define BANK2_INT_STS           ADDR_OFFSET(12)      //  Interrupt Status Register (8 bit, Read Only)
#define BANK2_INT_ACK           ADDR_OFFSET(12)      //  Interrupt Ack Register (8 bit, Write Only)

//Bank 3 Registers
#define BANK3_MT01              ADDR_OFFSET(0)       //  Multicast Hash Table 0-1
#define BANK3_MT23              ADDR_OFFSET(2)       //  Multicast Hash Table 2-3
#define BANK3_MT45              ADDR_OFFSET(4)       //  Multicast Hash Table 4-5
#define BANK3_MT67              ADDR_OFFSET(6)       //  Multicast Hash Table 6-7
#define BANK3_MGMT              ADDR_OFFSET(8)       //  PHY management
#define BANK3_REV               ADDR_OFFSET(10)      //  Chip Id/Revision
#define BANK3_ERCV              ADDR_OFFSET(12)      //  Early receive configuration

//Masks for Transmit Control Register (BANK0_TCR)
#define TCR_FDSE                0x8000  //  Full Duplex Switched Ethernet
#define TCR_ETEN_TYPE           0x4000
#define TCR_EPH_LOOP            0x2000  //  Loop at EPH block
#define TCR_STP_SQET            0x1000  //  Stop xmit on SQET error
#define TCR_FDUPLX              0x0800  //  Full duplex mode
#define TCR_MON_CSN             0x0400  //  Monitor carrier
#define TCR_NO_CRC              0x0100  //  Don't append CRC
#define TCR_PAD_EN              0x0080  //  Pad short frames
#define TCR_TXP_EN              0x0008
#define TCR_FOR_COL             0x0004  //  Force collision
#define TCR_LOOP                0x0002  //  Local loopback
#define TCR_TX_ENA              0x0001  //  Enable transmitter

//Masks for Receive Control Register (BANK0_RCR)
#define RCR_RESET               0x8000  //  Software reset
#define RCR_FILT_CAR            0x4000  //  Filter carrier for 12 bits