📄 platform.inc
字号:
;
; The content of this file or document is CONFIDENTIAL and PROPRIETARY
; to Jade Technologies Co., Ltd. It is subjected to the terms of a
; License Agreement between Licensee and Jade Technologies Co., Ltd.
; restricting among other things, the use, reproduction, distribution
; and transfer. Each of the embodiments, including this information
; and any derivative work shall retain this copyright notice.
;
; Copyright (c) 2004 - 2005 Jade Technologies Co., Ltd.
; All rights reserved.
;
; ----------------------------------------------------------------
; File: platform.inc,v
; Revision: 1.0
; ----------------------------------------------------------------
; $
;
; Z228 address map
;
;
;***********************************************************************/
INCLUDE sizes.inc
IF :LNOT: :DEF: __platform_inc
__platform_inc EQU 1
;-------------------------------------------------------------------------------
; Physical memory / device address's
;-------------------------------------------------------------------------------
;
PHYS_RAM_BASE EQU 0x00000000 ; SDRAM base address
PHYS_DMA_LIST_BASE EQU 0x03E80000 ; DMA list base in SDRAM
PHYS_CLCD_BUFF_BASE EQU 0x03F00000 ; Frame Buffer in SDRAM
PHYS_SYS_REGISTER_BASE EQU 0x20000000 ; System registers
PHYS_AACI_BASE EQU 0x20037000 ; Advanced Audio CODEC Interface
PHYS_MMCI0_BASE EQU 0x20039000 ; MultiMedia Card Interface 0
PHYS_MMCI1_BASE EQU 0x2003B000 ; MMC Interface 1
PHYS_68KBUS_BASE EQU 0x20004000 ; 68K BUS
PHYS_ETHERNET_BASE EQU PHYS_68KBUS_BASE ; Ethernet
PHYS_USB_BASE EQU 0x20080000 ; Universal Serial Bus
PHYS_CF_BASE EQU 0x2000E000 ;CF CARD
PHYS_SSMC_CNTL_BASE EQU 0x2000F000 ; Synchronous Static Memory Controller
PHYS_MPMC_CNTL_BASE EQU 0X2000D000 ; MultiPort Memory Controller
PHYS_CLCD_CNTL_BASE EQU 0X20002000 ; Color LCD Controller
PHYS_DMA_BASE EQU 0X20001000 ; Dynamic Memory Access Controller
PHYS_DMA2_BASE EQU 0X20011000 ; Dynamic Memory Access Controller2
PHYS_VIC_BASE EQU 0x20010000 ; Vectored Interrupt Controller
PHYS_SC_BASE EQU 0x20020000 ; System Controller
PHYS_WDOG_BASE EQU 0x20021000 ; Watchdog
PHYS_CT_BASE EQU 0x20022000 ; Counter/Timers 0 & 1
PHYS_CT2_BASE EQU 0x20023000 ; Counter/Timers 2 & 3
PHYS_GPIO0_BASE EQU 0x20024000 ; General Purpose Input/Output 0
PHYS_GPIO1_BASE EQU 0x20025000 ; GPIO 1
PHYS_GPIO2_BASE EQU 0x20026000 ; GPIO 2
PHYS_GPIO3_BASE EQU 0x20027000 ; GPIO 3
PHYS_GPIO4_BASE EQU 0x2002B000
PHYS_GPIO5_BASE EQU 0x2002C000
PHYS_GPIO6_BASE EQU 0x2002D000
PHYS_GPIO7_BASE EQU 0x2002E000
PHYS_GPIO8_BASE EQU 0x2002F000
PHYS_RTC_BASE EQU 0x20028000 ; Real Time Clock
PHYS_SCI_BASE EQU 0x20038000 ; Smart Card base
PHYS_UART0_BASE EQU 0x20030000 ; Universal Asynchronous Receive/Transmit 0 ;Debug Output
PHYS_UART1_BASE EQU 0x20031000 ; UART 1
PHYS_UART2_BASE EQU 0x20032000 ; UART 2
PHYS_UART3_BASE EQU 0x20033000 ; UART 3
PHYS_SSP_BASE EQU 0x20034000 ; Synchronous Serial Port
PHYS_SSP1_BASE EQU 0x20035000 ; Synchronous Serial Port1
PHYS_FLASH_BASE EQU 0xC4000000 ; Flash memory
;-------------------------------------------------------------------------------
; Z228 Development Board Flash settings
;-------------------------------------------------------------------------------
; The following settings are a reflection of those found in platform.h
; They MUST be kept in sync.
ARMVPB_FLASH_SIZE EQU SZ_32M
ARMVPB_FLASH_END EQU (PHYS_FLASH_BASE + ARMVPB_FLASH_SIZE - 1)
ARMVPB_FLASH_BLOCK_SIZE EQU SZ_128K
;-------------------------------------------------------------------------------
; Stack space for EBoot
;-------------------------------------------------------------------------------
;
; First 32K of memory is free (must match config.bib free space) for use
; temporarily as a stack for Eboot
;
TEMP_STACK_BASE EQU (PHYS_RAM_BASE + SZ_32K - 4)
;-------------------------------------------------------------------------------
; VIRTUAL ADDRESSES
;-------------------------------------------------------------------------------
; The following are the virtual address mappings which have a 512Mb range and
; are either positioned in the cached memory space from 0x80000000 to 0x9FFFFFFF
; or, for devices, the uncached range of memory from 0xA0000000 to 0xBFFFFFFF.
; But the ranges are overlayed so that they share a 512Mb address range of
; 0x00000000 to 0x1FFFFFFF (i.e. a mask of 0x1FFFFFFF is applied to the values
; below).
;
; System Flash
;
; Virtual address range of 0x00000000 to 0x03FFFFFF (64Mb)
;
VA_FLASH_BASE EQU 0x80000000 ; Flash, 64Mb
; System RAM
;
; Allow space for the RAM to grow up 128Mb. NOTE, however, that we
; can only declare RAM for the minimum amount of memory possible in
; a system, because the kernel uses the very top of RAM for its own
; structures
;
; Virtual address range of 0x08000000 to 0x0FFFFFFF (128Mb)
;
VA_RAM_BASE EQU 0x88000000
;
; ARM Color LCD
;
; Virtual address range of 0x06000000 to 0x060FFFFF (1Mb)
;
VA_CLCD_BUFF_BASE EQU 0xa6000000 ; Frame Buffer
; VA 0x06100000 -> 0x07FFFFFF unused
;
; Include entries for those devices which are (potentially) used in
; the OAL
;
; Various devices and controllers
;
; Virtual address range of 0x02000000 to 0x020FFFFF (1Mb)
;
VA_HDR_BASE EQU 0xa2000000 ; VP peripherals base, 1Mb
VA_68KBUS_OFFSET EQU 0x00040000 ; M68K BUS */
VA_EDBG_OFFSET EQU VA_68KBUS_OFFSET ; Ethernet Debug
VA_EDBG_BASE EQU (VA_HDR_BASE + VA_EDBG_OFFSET)
; Virtual address range of 0x04000000 to 0x040FFFFF (1Mb)
;
VA_CT_OFFSET EQU 0x00022000 ; Counter/Timers 0 & 1
VA_UART0_OFFSET EQU 0x00030000 ; UART 0 - affects entry in serial.reg
VA_UART1_OFFSET EQU 0x00031000 ; UART 1 - affects entry in serial.reg
VA_UART2_OFFSET EQU 0x00032000 ; UART 2
VA_UART3_OFFSET EQU 0x00033000
VA_RTC_OFFSET EQU 0x00028000 ; Real-time clock
VA_VIC_OFFSET EQU 0x00010000 ; Vectored Interrupt Controller
VA_DMA_OFFSET EQU 0x00001000 ; Virtual address for DMA
VA_SC_OFFSET EQU 0x000e0000 ; System Controller
VA_CT_BASE EQU (VA_HDR_BASE + VA_CT_OFFSET)
VA_UART0_BASE EQU (VA_HDR_BASE + VA_UART0_OFFSET)
VA_UART1_BASE EQU (VA_HDR_BASE + VA_UART1_OFFSET)
VA_UART2_BASE EQU (VA_HDR_BASE + VA_UART2_OFFSET)
VA_RTC_BASE EQU (VA_HDR_BASE + VA_RTC_OFFSET)
VA_VIC_BASE EQU (VA_HDR_BASE + VA_VIC_OFFSET)
VA_DMA_BASE EQU (VA_HDR_BASE + VA_DMA_OFFSET)
VA_SC_BASE EQU (VA_HDR_BASE + VA_SC_OFFSET)
; VA 0x02100000 -> 0x3FFFFFFF unused
; VA 0x04100000 -> 0x5FFFFFFF unused
;-------------------------------------------------------------------------------
; Interrupt Controller
;-------------------------------------------------------------------------------
;
; Interrupt numbers
; (refer to intx20t.c when making changes here.)
; The following mappings are for the VIC - on the chip
IRQ_VIC_WDOG EQU 0
IRQ_VIC_SOFTINT EQU 1
IRQ_VIC_CPUINT0 EQU 2
IRQ_VIC_CPUINT1 EQU 3
IRQ_VIC_TIMER0 EQU 4
IRQ_VIC_TIMER1 EQU 4
IRQ_VIC_TIMER2 EQU 5
IRQ_VIC_TIMER3 EQU 5
IRQ_VIC_GPIO2 EQU 6
IRQ_VIC_IIC EQU 7
IRQ_VIC_CF EQU 8
IRQ_VIC_RTC EQU 9
IRQ_VIC_USB EQU 10
IRQ_VIC_UART0 EQU 11
IRQ_VIC_UART1 EQU 12
IRQ_VIC_UART2 EQU 13
IRQ_VIC_UART3 EQU 14
IRQ_VIC_SCI EQU 15
IRQ_VIC_CLCD EQU 16
IRQ_VIC_DMA EQU 17
IRQ_VIC_PWRFAIL EQU 18
IRQ_VIC_SSP EQU 19
IRQ_VIC_GPIO7 EQU 20
IRQ_VIC_GPIO8_3 EQU 21
IRQ_VIC_KMI EQU 22
IRQ_VIC_AACI EQU 23
IRQ_VIC_CLCD1 EQU 24
IRQ_VIC_GPIO8_5 EQU 25
IRQ_VIC_GPIO0 EQU 26
IRQ_VIC_VIA EQU 27
IRQ_VIC_MP4D EQU 28
IRQ_VIC_MP4E EQU 29
IRQ_VIC_GPIO8_0 EQU 30
IRQ_VIC_GPIO8_1 EQU 31
IRQ_VIC_GND EQU 32
ENDIF ; __platform_inc
END
; /* EOF */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -